[v7,07/12] x86/resctrl: Add sysfs interface to read mbm_total_bytes event configuration
Message ID | 166604561380.5345.17668177010598977321.stgit@bmoger-ubuntu |
---|---|
State | New |
Headers |
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Mon, 17 Oct 2022 17:26:59 -0500 Subject: [PATCH v7 07/12] x86/resctrl: Add sysfs interface to read mbm_total_bytes event configuration From: Babu Moger <babu.moger@amd.com> To: <corbet@lwn.net>, <reinette.chatre@intel.com>, <tglx@linutronix.de>, <mingo@redhat.com>, <bp@alien8.de> CC: <fenghua.yu@intel.com>, <dave.hansen@linux.intel.com>, <x86@kernel.org>, <hpa@zytor.com>, <paulmck@kernel.org>, <akpm@linux-foundation.org>, <quic_neeraju@quicinc.com>, <rdunlap@infradead.org>, <damien.lemoal@opensource.wdc.com>, <songmuchun@bytedance.com>, <peterz@infradead.org>, <jpoimboe@kernel.org>, <pbonzini@redhat.com>, <babu.moger@amd.com>, <chang.seok.bae@intel.com>, <pawan.kumar.gupta@linux.intel.com>, <jmattson@google.com>, <daniel.sneddon@linux.intel.com>, <sandipan.das@amd.com>, <tony.luck@intel.com>, <james.morse@arm.com>, <linux-doc@vger.kernel.org>, <linux-kernel@vger.kernel.org>, <bagasdotme@gmail.com>, <eranian@google.com> Date: Mon, 17 Oct 2022 17:26:53 -0500 Message-ID: <166604561380.5345.17668177010598977321.stgit@bmoger-ubuntu> In-Reply-To: <166604543832.5345.9696970469830919982.stgit@bmoger-ubuntu> References: <166604543832.5345.9696970469830919982.stgit@bmoger-ubuntu> User-Agent: StGit/1.1.dev103+g5369f4c MIME-Version: 1.0 Content-Type: text/plain; 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x86/resctrl: Support for AMD QoS new features
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Commit Message
Moger, Babu
Oct. 17, 2022, 10:26 p.m. UTC
The current event configuration can be viewed by the user by reading
the configuration file /sys/fs/resctrl/info/L3_MON/mbm_total_config.
The event configuration settings are domain specific and will affect all
the CPUs in the domain.
Following are the types of events supported:
==== ===========================================================
Bits Description
==== ===========================================================
6 Dirty Victims from the QOS domain to all types of memory
5 Reads to slow memory in the non-local NUMA domain
4 Reads to slow memory in the local NUMA domain
3 Non-temporal writes to non-local NUMA domain
2 Non-temporal writes to local NUMA domain
1 Reads to memory in the non-local NUMA domain
0 Reads to memory in the local NUMA domain
==== ===========================================================
By default, the mbm_total_bytes configuration is set to 0x7f to count
all the event types.
For example:
$cat /sys/fs/resctrl/info/L3_MON/mbm_total_config
0=0x7f;1=0x7f;2=0x7f;3=0x7f
In this case, the event mbm_total_bytes is currently configured
with 0x7f on domains 0 to 3.
Signed-off-by: Babu Moger <babu.moger@amd.com>
---
arch/x86/kernel/cpu/resctrl/core.c | 3 +
arch/x86/kernel/cpu/resctrl/internal.h | 2 +
arch/x86/kernel/cpu/resctrl/rdtgroup.c | 76 ++++++++++++++++++++++++++++++++
3 files changed, 81 insertions(+)
Comments
Hi Babu, On 10/17/2022 3:26 PM, Babu Moger wrote: > The current event configuration can be viewed by the user by reading > the configuration file /sys/fs/resctrl/info/L3_MON/mbm_total_config. > The event configuration settings are domain specific and will affect all > the CPUs in the domain. > > Following are the types of events supported: > ==== =========================================================== > Bits Description > ==== =========================================================== > 6 Dirty Victims from the QOS domain to all types of memory > 5 Reads to slow memory in the non-local NUMA domain > 4 Reads to slow memory in the local NUMA domain > 3 Non-temporal writes to non-local NUMA domain > 2 Non-temporal writes to local NUMA domain > 1 Reads to memory in the non-local NUMA domain > 0 Reads to memory in the local NUMA domain > ==== =========================================================== > > By default, the mbm_total_bytes configuration is set to 0x7f to count > all the event types. > > For example: > $cat /sys/fs/resctrl/info/L3_MON/mbm_total_config > 0=0x7f;1=0x7f;2=0x7f;3=0x7f > > In this case, the event mbm_total_bytes is currently configured > with 0x7f on domains 0 to 3. > > Signed-off-by: Babu Moger <babu.moger@amd.com> > --- > arch/x86/kernel/cpu/resctrl/core.c | 3 + > arch/x86/kernel/cpu/resctrl/internal.h | 2 + > arch/x86/kernel/cpu/resctrl/rdtgroup.c | 76 ++++++++++++++++++++++++++++++++ > 3 files changed, 81 insertions(+) > > diff --git a/arch/x86/kernel/cpu/resctrl/core.c b/arch/x86/kernel/cpu/resctrl/core.c > index 46813b1c50c2..758c5d7553a4 100644 > --- a/arch/x86/kernel/cpu/resctrl/core.c > +++ b/arch/x86/kernel/cpu/resctrl/core.c > @@ -826,6 +826,9 @@ static __init bool get_rdt_mon_resources(void) > if (!rdt_mon_features) > return false; > > + if (mon_configurable) > + mbm_config_rftype_init(); > + Please move this to be within rdt_get_mon_l3_config(). > return !rdt_get_mon_l3_config(r, mon_configurable); > } > > diff --git a/arch/x86/kernel/cpu/resctrl/internal.h b/arch/x86/kernel/cpu/resctrl/internal.h > index b458f768f30c..326a1b582f38 100644 > --- a/arch/x86/kernel/cpu/resctrl/internal.h > +++ b/arch/x86/kernel/cpu/resctrl/internal.h > @@ -15,6 +15,7 @@ > #define MSR_IA32_MBA_THRTL_BASE 0xd50 > #define MSR_IA32_MBA_BW_BASE 0xc0000200 > #define MSR_IA32_SMBA_BW_BASE 0xc0000280 > +#define MSR_IA32_EVT_CFG_BASE 0xc0000400 > > #define MSR_IA32_QM_CTR 0x0c8e > #define MSR_IA32_QM_EVTSEL 0x0c8d > @@ -541,5 +542,6 @@ bool has_busy_rmid(struct rdt_resource *r, struct rdt_domain *d); > void __check_limbo(struct rdt_domain *d, bool force_free); > void rdt_domain_reconfigure_cdp(struct rdt_resource *r); > void __init thread_throttle_mode_init(void); > +void __init mbm_config_rftype_init(void); > > #endif /* _ASM_X86_RESCTRL_INTERNAL_H */ > diff --git a/arch/x86/kernel/cpu/resctrl/rdtgroup.c b/arch/x86/kernel/cpu/resctrl/rdtgroup.c > index 5f0ef1bf4c78..0982845594d0 100644 > --- a/arch/x86/kernel/cpu/resctrl/rdtgroup.c > +++ b/arch/x86/kernel/cpu/resctrl/rdtgroup.c > @@ -1423,6 +1423,67 @@ static int rdtgroup_size_show(struct kernfs_open_file *of, > return ret; > } > > +struct mon_config_info { > + u32 evtid; > + u32 mon_config; > +}; > + > +static void mon_event_config_read(void *info) > +{ > + struct mon_config_info *mon_info = info; > + u32 h, msr_index; > + > + switch (mon_info->evtid) { > + case QOS_L3_MBM_TOTAL_EVENT_ID: > + msr_index = 0; > + break; > + case QOS_L3_MBM_LOCAL_EVENT_ID: > + msr_index = 1; > + break; > + default: > + /* Not expected to come here */ > + return; > + } > + > + rdmsr(MSR_IA32_EVT_CFG_BASE + msr_index, mon_info->mon_config, h); > +} > + > +static void mondata_config_read(struct rdt_domain *d, struct mon_config_info *mon_info) > +{ > + smp_call_function_any(&d->cpu_mask, mon_event_config_read, mon_info, 1); > +} > + > +static int mbm_config_show(struct seq_file *s, struct rdt_resource *r, u32 evtid) > +{ > + struct mon_config_info mon_info = {0}; > + struct rdt_domain *dom; > + bool sep = false; > + > + list_for_each_entry(dom, &r->domains, list) { This is done with no protection ... I do not see anything preventing last CPU of a domain going offline around this time taking this domain with it while this code still tries to access its members. I think all of this needs protection with rdtgroup_mutex. > + if (sep) > + seq_puts(s, ";"); > + > + mon_info.evtid = evtid; > + mondata_config_read(dom, &mon_info); > + > + seq_printf(s, "%d=0x%02x", dom->id, mon_info.mon_config); It does not seem robust to me to use printf field width to manage the data returned from hardware. At this time bits 0 - 6 are supported by hardware ... what happens if hardware starts using bit 7 for something? It seems to me that the mask introduced later needs to be pulled here to ensure that only the valid bits are handled. > + sep = true; > + } > + seq_puts(s, "\n"); > + > + return 0; > +} > + > +static int mbm_total_config_show(struct kernfs_open_file *of, > + struct seq_file *seq, void *v) > +{ > + struct rdt_resource *r = of->kn->parent->priv; > + > + mbm_config_show(seq, r, QOS_L3_MBM_TOTAL_EVENT_ID); > + > + return 0; > +} > + > /* rdtgroup information files for one cache resource. */ > static struct rftype res_common_files[] = { > { > @@ -1521,6 +1582,12 @@ static struct rftype res_common_files[] = { > .seq_show = max_threshold_occ_show, > .fflags = RF_MON_INFO | RFTYPE_RES_CACHE, > }, > + { > + .name = "mbm_total_config", > + .mode = 0644, > + .kf_ops = &rdtgroup_kf_single_ops, > + .seq_show = mbm_total_config_show, > + }, Please only make mode writable when there is support for it. > { > .name = "cpus", > .mode = 0644, > @@ -1627,6 +1694,15 @@ void __init thread_throttle_mode_init(void) > rft->fflags = RF_CTRL_INFO | RFTYPE_RES_MB; > } > > +void __init mbm_config_rftype_init(void) > +{ > + struct rftype *rft; > + > + rft = rdtgroup_get_rftype_by_name("mbm_total_config"); > + if (rft) > + rft->fflags = RF_MON_INFO | RFTYPE_RES_CACHE; > +} > + > /** > * rdtgroup_kn_mode_restrict - Restrict user access to named resctrl file > * @r: The resource group with which the file is associated. > > Reinette
Hi Reinette, On 10/25/22 18:47, Reinette Chatre wrote: > Hi Babu, > > On 10/17/2022 3:26 PM, Babu Moger wrote: >> The current event configuration can be viewed by the user by reading >> the configuration file /sys/fs/resctrl/info/L3_MON/mbm_total_config. >> The event configuration settings are domain specific and will affect all >> the CPUs in the domain. >> >> Following are the types of events supported: >> ==== =========================================================== >> Bits Description >> ==== =========================================================== >> 6 Dirty Victims from the QOS domain to all types of memory >> 5 Reads to slow memory in the non-local NUMA domain >> 4 Reads to slow memory in the local NUMA domain >> 3 Non-temporal writes to non-local NUMA domain >> 2 Non-temporal writes to local NUMA domain >> 1 Reads to memory in the non-local NUMA domain >> 0 Reads to memory in the local NUMA domain >> ==== =========================================================== >> >> By default, the mbm_total_bytes configuration is set to 0x7f to count >> all the event types. >> >> For example: >> $cat /sys/fs/resctrl/info/L3_MON/mbm_total_config >> 0=0x7f;1=0x7f;2=0x7f;3=0x7f >> >> In this case, the event mbm_total_bytes is currently configured >> with 0x7f on domains 0 to 3. >> >> Signed-off-by: Babu Moger <babu.moger@amd.com> >> --- >> arch/x86/kernel/cpu/resctrl/core.c | 3 + >> arch/x86/kernel/cpu/resctrl/internal.h | 2 + >> arch/x86/kernel/cpu/resctrl/rdtgroup.c | 76 ++++++++++++++++++++++++++++++++ >> 3 files changed, 81 insertions(+) >> >> diff --git a/arch/x86/kernel/cpu/resctrl/core.c b/arch/x86/kernel/cpu/resctrl/core.c >> index 46813b1c50c2..758c5d7553a4 100644 >> --- a/arch/x86/kernel/cpu/resctrl/core.c >> +++ b/arch/x86/kernel/cpu/resctrl/core.c >> @@ -826,6 +826,9 @@ static __init bool get_rdt_mon_resources(void) >> if (!rdt_mon_features) >> return false; >> >> + if (mon_configurable) >> + mbm_config_rftype_init(); >> + > Please move this to be within rdt_get_mon_l3_config(). Sure. > >> return !rdt_get_mon_l3_config(r, mon_configurable); >> } >> >> diff --git a/arch/x86/kernel/cpu/resctrl/internal.h b/arch/x86/kernel/cpu/resctrl/internal.h >> index b458f768f30c..326a1b582f38 100644 >> --- a/arch/x86/kernel/cpu/resctrl/internal.h >> +++ b/arch/x86/kernel/cpu/resctrl/internal.h >> @@ -15,6 +15,7 @@ >> #define MSR_IA32_MBA_THRTL_BASE 0xd50 >> #define MSR_IA32_MBA_BW_BASE 0xc0000200 >> #define MSR_IA32_SMBA_BW_BASE 0xc0000280 >> +#define MSR_IA32_EVT_CFG_BASE 0xc0000400 >> >> #define MSR_IA32_QM_CTR 0x0c8e >> #define MSR_IA32_QM_EVTSEL 0x0c8d >> @@ -541,5 +542,6 @@ bool has_busy_rmid(struct rdt_resource *r, struct rdt_domain *d); >> void __check_limbo(struct rdt_domain *d, bool force_free); >> void rdt_domain_reconfigure_cdp(struct rdt_resource *r); >> void __init thread_throttle_mode_init(void); >> +void __init mbm_config_rftype_init(void); >> >> #endif /* _ASM_X86_RESCTRL_INTERNAL_H */ >> diff --git a/arch/x86/kernel/cpu/resctrl/rdtgroup.c b/arch/x86/kernel/cpu/resctrl/rdtgroup.c >> index 5f0ef1bf4c78..0982845594d0 100644 >> --- a/arch/x86/kernel/cpu/resctrl/rdtgroup.c >> +++ b/arch/x86/kernel/cpu/resctrl/rdtgroup.c >> @@ -1423,6 +1423,67 @@ static int rdtgroup_size_show(struct kernfs_open_file *of, >> return ret; >> } >> >> +struct mon_config_info { >> + u32 evtid; >> + u32 mon_config; >> +}; >> + >> +static void mon_event_config_read(void *info) >> +{ >> + struct mon_config_info *mon_info = info; >> + u32 h, msr_index; >> + >> + switch (mon_info->evtid) { >> + case QOS_L3_MBM_TOTAL_EVENT_ID: >> + msr_index = 0; >> + break; >> + case QOS_L3_MBM_LOCAL_EVENT_ID: >> + msr_index = 1; >> + break; >> + default: >> + /* Not expected to come here */ >> + return; >> + } >> + >> + rdmsr(MSR_IA32_EVT_CFG_BASE + msr_index, mon_info->mon_config, h); >> +} >> + >> +static void mondata_config_read(struct rdt_domain *d, struct mon_config_info *mon_info) >> +{ >> + smp_call_function_any(&d->cpu_mask, mon_event_config_read, mon_info, 1); >> +} >> + >> +static int mbm_config_show(struct seq_file *s, struct rdt_resource *r, u32 evtid) >> +{ >> + struct mon_config_info mon_info = {0}; >> + struct rdt_domain *dom; >> + bool sep = false; >> + >> + list_for_each_entry(dom, &r->domains, list) { > This is done with no protection ... I do not see anything preventing last CPU of > a domain going offline around this time taking this domain with it while this code > still tries to access its members. > > I think all of this needs protection with rdtgroup_mutex. Yes. I agree. Will change it. > >> + if (sep) >> + seq_puts(s, ";"); >> + >> + mon_info.evtid = evtid; >> + mondata_config_read(dom, &mon_info); >> + >> + seq_printf(s, "%d=0x%02x", dom->id, mon_info.mon_config); > It does not seem robust to me to use printf field width to manage the data > returned from hardware. At this time bits 0 - 6 are supported by hardware ... > what happens if hardware starts using bit 7 for something? > It seems to me that the mask introduced later needs to be pulled here to > ensure that only the valid bits are handled. Ok. Sure. > >> + sep = true; >> + } >> + seq_puts(s, "\n"); >> + >> + return 0; >> +} >> + >> +static int mbm_total_config_show(struct kernfs_open_file *of, >> + struct seq_file *seq, void *v) >> +{ >> + struct rdt_resource *r = of->kn->parent->priv; >> + >> + mbm_config_show(seq, r, QOS_L3_MBM_TOTAL_EVENT_ID); >> + >> + return 0; >> +} >> + >> /* rdtgroup information files for one cache resource. */ >> static struct rftype res_common_files[] = { >> { >> @@ -1521,6 +1582,12 @@ static struct rftype res_common_files[] = { >> .seq_show = max_threshold_occ_show, >> .fflags = RF_MON_INFO | RFTYPE_RES_CACHE, >> }, >> + { >> + .name = "mbm_total_config", >> + .mode = 0644, >> + .kf_ops = &rdtgroup_kf_single_ops, >> + .seq_show = mbm_total_config_show, >> + }, > Please only make mode writable when there is support for it. Ok. Thanks Babu > >> { >> .name = "cpus", >> .mode = 0644, >> @@ -1627,6 +1694,15 @@ void __init thread_throttle_mode_init(void) >> rft->fflags = RF_CTRL_INFO | RFTYPE_RES_MB; >> } >> >> +void __init mbm_config_rftype_init(void) >> +{ >> + struct rftype *rft; >> + >> + rft = rdtgroup_get_rftype_by_name("mbm_total_config"); >> + if (rft) >> + rft->fflags = RF_MON_INFO | RFTYPE_RES_CACHE; >> +} >> + >> /** >> * rdtgroup_kn_mode_restrict - Restrict user access to named resctrl file >> * @r: The resource group with which the file is associated. >> >> > > Reinette
diff --git a/arch/x86/kernel/cpu/resctrl/core.c b/arch/x86/kernel/cpu/resctrl/core.c index 46813b1c50c2..758c5d7553a4 100644 --- a/arch/x86/kernel/cpu/resctrl/core.c +++ b/arch/x86/kernel/cpu/resctrl/core.c @@ -826,6 +826,9 @@ static __init bool get_rdt_mon_resources(void) if (!rdt_mon_features) return false; + if (mon_configurable) + mbm_config_rftype_init(); + return !rdt_get_mon_l3_config(r, mon_configurable); } diff --git a/arch/x86/kernel/cpu/resctrl/internal.h b/arch/x86/kernel/cpu/resctrl/internal.h index b458f768f30c..326a1b582f38 100644 --- a/arch/x86/kernel/cpu/resctrl/internal.h +++ b/arch/x86/kernel/cpu/resctrl/internal.h @@ -15,6 +15,7 @@ #define MSR_IA32_MBA_THRTL_BASE 0xd50 #define MSR_IA32_MBA_BW_BASE 0xc0000200 #define MSR_IA32_SMBA_BW_BASE 0xc0000280 +#define MSR_IA32_EVT_CFG_BASE 0xc0000400 #define MSR_IA32_QM_CTR 0x0c8e #define MSR_IA32_QM_EVTSEL 0x0c8d @@ -541,5 +542,6 @@ bool has_busy_rmid(struct rdt_resource *r, struct rdt_domain *d); void __check_limbo(struct rdt_domain *d, bool force_free); void rdt_domain_reconfigure_cdp(struct rdt_resource *r); void __init thread_throttle_mode_init(void); +void __init mbm_config_rftype_init(void); #endif /* _ASM_X86_RESCTRL_INTERNAL_H */ diff --git a/arch/x86/kernel/cpu/resctrl/rdtgroup.c b/arch/x86/kernel/cpu/resctrl/rdtgroup.c index 5f0ef1bf4c78..0982845594d0 100644 --- a/arch/x86/kernel/cpu/resctrl/rdtgroup.c +++ b/arch/x86/kernel/cpu/resctrl/rdtgroup.c @@ -1423,6 +1423,67 @@ static int rdtgroup_size_show(struct kernfs_open_file *of, return ret; } +struct mon_config_info { + u32 evtid; + u32 mon_config; +}; + +static void mon_event_config_read(void *info) +{ + struct mon_config_info *mon_info = info; + u32 h, msr_index; + + switch (mon_info->evtid) { + case QOS_L3_MBM_TOTAL_EVENT_ID: + msr_index = 0; + break; + case QOS_L3_MBM_LOCAL_EVENT_ID: + msr_index = 1; + break; + default: + /* Not expected to come here */ + return; + } + + rdmsr(MSR_IA32_EVT_CFG_BASE + msr_index, mon_info->mon_config, h); +} + +static void mondata_config_read(struct rdt_domain *d, struct mon_config_info *mon_info) +{ + smp_call_function_any(&d->cpu_mask, mon_event_config_read, mon_info, 1); +} + +static int mbm_config_show(struct seq_file *s, struct rdt_resource *r, u32 evtid) +{ + struct mon_config_info mon_info = {0}; + struct rdt_domain *dom; + bool sep = false; + + list_for_each_entry(dom, &r->domains, list) { + if (sep) + seq_puts(s, ";"); + + mon_info.evtid = evtid; + mondata_config_read(dom, &mon_info); + + seq_printf(s, "%d=0x%02x", dom->id, mon_info.mon_config); + sep = true; + } + seq_puts(s, "\n"); + + return 0; +} + +static int mbm_total_config_show(struct kernfs_open_file *of, + struct seq_file *seq, void *v) +{ + struct rdt_resource *r = of->kn->parent->priv; + + mbm_config_show(seq, r, QOS_L3_MBM_TOTAL_EVENT_ID); + + return 0; +} + /* rdtgroup information files for one cache resource. */ static struct rftype res_common_files[] = { { @@ -1521,6 +1582,12 @@ static struct rftype res_common_files[] = { .seq_show = max_threshold_occ_show, .fflags = RF_MON_INFO | RFTYPE_RES_CACHE, }, + { + .name = "mbm_total_config", + .mode = 0644, + .kf_ops = &rdtgroup_kf_single_ops, + .seq_show = mbm_total_config_show, + }, { .name = "cpus", .mode = 0644, @@ -1627,6 +1694,15 @@ void __init thread_throttle_mode_init(void) rft->fflags = RF_CTRL_INFO | RFTYPE_RES_MB; } +void __init mbm_config_rftype_init(void) +{ + struct rftype *rft; + + rft = rdtgroup_get_rftype_by_name("mbm_total_config"); + if (rft) + rft->fflags = RF_MON_INFO | RFTYPE_RES_CACHE; +} + /** * rdtgroup_kn_mode_restrict - Restrict user access to named resctrl file * @r: The resource group with which the file is associated.