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[19/23] arm64: zynqmp: Enable DP driver for SOMs

Message ID	15d16b4de933bfae108df6ca368eb2cdf916aa02.1683034376.git.michal.simek@amd.com
State	New
Headers	Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) client-ip=2620:137:e000::1:20; Received-SPF: Pass (protection.outlook.com: domain of amd.com designates 165.204.84.17 as permitted sender) receiver=protection.outlook.com; client-ip=165.204.84.17; helo=SATLEXMB04.amd.com; pr=C From: Michal Simek <michal.simek@amd.com> To: <linux-kernel@vger.kernel.org>, <monstr@monstr.eu>, <michal.simek@xilinx.com>, <git@xilinx.com> CC: Andrew Davis <afd@ti.com>, Ashok Reddy Soma <ashok.reddy.soma@xilinx.com>, Geert Uytterhoeven <geert+renesas@glider.be>, Krzysztof Kozlowski <krzysztof.kozlowski+dt@linaro.org>, Rob Herring <robh+dt@kernel.org>, <devicetree@vger.kernel.org>, <linux-arm-kernel@lists.infradead.org> Subject: [PATCH 19/23] arm64: zynqmp: Enable DP driver for SOMs Date: Tue, 2 May 2023 15:35:47 +0200 Message-ID: <15d16b4de933bfae108df6ca368eb2cdf916aa02.1683034376.git.michal.simek@amd.com> In-Reply-To: <cover.1683034376.git.michal.simek@amd.com> References: <cover.1683034376.git.michal.simek@amd.com> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Content-Type: text/plain Precedence: bulk
Series	arm64: zynqmp: Misc zynqmp changes \| [00/23] arm64: zynqmp: Misc zynqmp changes [01/23] arm64: zynqmp: Describe TI phy as ethernet-phy-id [02/23] arm64: zynqmp: Fix usb node drive strength and slew rate [03/23] arm64: zynqmp: Set qspi tx-buswidth to 4 [04/23] arm64: zynqmp: Fix usb reset over bootmode pins on zcu100 [05/23] arm64: zynqmp: Add L2 cache nodes [06/23] arm64: zynqmp: Sync node name address with reg (mailbox) [07/23] arm64: zynqmp: Add pmu interrupt-affinity [08/23] arm64: zynqmp: Add resets property to sdhci nodes [09/23] arm64: zynqmp: Add dmas, dp, rtc, watchdogs and opp nodes for SOM [10/23] arm64: zynqmp: Add linux,code for gpio button [11/23] arm64: zynqmp: Use assigned-clock-rates for setting up SD clock in SOM [12/23] arm64: zynqmp: Add mtd partition for secure OS storage area [13/23] arm64: zynqmp: Used fixed-partitions for QSPI in k26 [14/23] arm64: zynqmp: Add gpio labels for modepin gpio [15/23] arm64: zynqmp: Add pinctrl emmc description to SM-K26 [16/23] arm64: zynqmp: Disable USB3.0 for zc1751-xm016-dc2 [17/23] arm64: zynqmp: Switch to ethernet-phy-id in kv260 [18/23] arm64: zynqmp: Setup clock for DP and DPDMA [19/23] arm64: zynqmp: Enable DP driver for SOMs [20/23] arm64: zynqmp: Rename ams_ps/pl node names [21/23] arm64: zynqmp: Enable AMS on SOM and other zcu10x boards [22/23] arm64: zynqmp: Describe bus-width for SD card on KV260 [23/23] arm64: zynqmp: Add phase tags marking

Commit Message

Michal Simek May 2, 2023, 1:35 p.m. UTC

  DP DMA is already enabled that's why there is no reason to keep DP
disabled.

Signed-off-by: Michal Simek <michal.simek@amd.com>
---

 arch/arm64/boot/dts/xilinx/zynqmp-sck-kv-g-revA.dtso | 2 +-
 arch/arm64/boot/dts/xilinx/zynqmp-sck-kv-g-revB.dtso | 2 +-
 2 files changed, 2 insertions(+), 2 deletions(-)

Comments

Michal Simek May 16, 2023, 11:09 a.m. UTC | #1

On 5/2/23 15:35, Michal Simek wrote:
> DP DMA is already enabled that's why there is no reason to keep DP
> disabled.
> 
> Signed-off-by: Michal Simek <michal.simek@amd.com>
> ---
> 
>   arch/arm64/boot/dts/xilinx/zynqmp-sck-kv-g-revA.dtso | 2 +-
>   arch/arm64/boot/dts/xilinx/zynqmp-sck-kv-g-revB.dtso | 2 +-
>   2 files changed, 2 insertions(+), 2 deletions(-)
> 
> diff --git a/arch/arm64/boot/dts/xilinx/zynqmp-sck-kv-g-revA.dtso b/arch/arm64/boot/dts/xilinx/zynqmp-sck-kv-g-revA.dtso
> index 4f18b3efcced..776444714fad 100644
> --- a/arch/arm64/boot/dts/xilinx/zynqmp-sck-kv-g-revA.dtso
> +++ b/arch/arm64/boot/dts/xilinx/zynqmp-sck-kv-g-revA.dtso
> @@ -96,7 +96,7 @@ &sata {
>   };
>   
>   &zynqmp_dpsub {
> -	status = "disabled";
> +	status = "okay";
>   	phy-names = "dp-phy0", "dp-phy1";
>   	phys = <&psgtr 1 PHY_TYPE_DP 0 0>, <&psgtr 0 PHY_TYPE_DP 1 0>;
>   	assigned-clock-rates = <27000000>, <25000000>, <300000000>;
> diff --git a/arch/arm64/boot/dts/xilinx/zynqmp-sck-kv-g-revB.dtso b/arch/arm64/boot/dts/xilinx/zynqmp-sck-kv-g-revB.dtso
> index 77bc806b15a1..78d082a11492 100644
> --- a/arch/arm64/boot/dts/xilinx/zynqmp-sck-kv-g-revB.dtso
> +++ b/arch/arm64/boot/dts/xilinx/zynqmp-sck-kv-g-revB.dtso
> @@ -77,7 +77,7 @@ &psgtr {
>   };
>   
>   &zynqmp_dpsub {
> -	status = "disabled";
> +	status = "okay";
>   	phy-names = "dp-phy0", "dp-phy1";
>   	phys = <&psgtr 1 PHY_TYPE_DP 0 0>, <&psgtr 0 PHY_TYPE_DP 1 0>;
>   	assigned-clock-rates = <27000000>, <25000000>, <300000000>;

Applied.
M

diff mbox series

Patch

diff --git a/arch/arm64/boot/dts/xilinx/zynqmp-sck-kv-g-revA.dtso b/arch/arm64/boot/dts/xilinx/zynqmp-sck-kv-g-revA.dtso
index 4f18b3efcced..776444714fad 100644
--- a/arch/arm64/boot/dts/xilinx/zynqmp-sck-kv-g-revA.dtso
+++ b/arch/arm64/boot/dts/xilinx/zynqmp-sck-kv-g-revA.dtso
@@ -96,7 +96,7 @@  &sata {
 };
 
 &zynqmp_dpsub {
-	status = "disabled";
+	status = "okay";
 	phy-names = "dp-phy0", "dp-phy1";
 	phys = <&psgtr 1 PHY_TYPE_DP 0 0>, <&psgtr 0 PHY_TYPE_DP 1 0>;
 	assigned-clock-rates = <27000000>, <25000000>, <300000000>;
diff --git a/arch/arm64/boot/dts/xilinx/zynqmp-sck-kv-g-revB.dtso b/arch/arm64/boot/dts/xilinx/zynqmp-sck-kv-g-revB.dtso
index 77bc806b15a1..78d082a11492 100644
--- a/arch/arm64/boot/dts/xilinx/zynqmp-sck-kv-g-revB.dtso
+++ b/arch/arm64/boot/dts/xilinx/zynqmp-sck-kv-g-revB.dtso
@@ -77,7 +77,7 @@  &psgtr {
 };
 
 &zynqmp_dpsub {
-	status = "disabled";
+	status = "okay";
 	phy-names = "dp-phy0", "dp-phy1";
 	phys = <&psgtr 1 PHY_TYPE_DP 0 0>, <&psgtr 0 PHY_TYPE_DP 1 0>;
 	assigned-clock-rates = <27000000>, <25000000>, <300000000>;