From patchwork Sat Feb 11 16:03:09 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Daniel Golle X-Patchwork-Id: 55841 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:adf:eb09:0:0:0:0:0 with SMTP id s9csp1556555wrn; Sat, 11 Feb 2023 08:09:45 -0800 (PST) X-Google-Smtp-Source: AK7set/30YKv1nmVCgACPCLD1nx5+a96vmsSX4pNKlz7fm/iVgvrABKQqkamQouV4KHhqjoDoQip X-Received: by 2002:a05:6a20:3955:b0:bc:ee04:275d with SMTP id r21-20020a056a20395500b000bcee04275dmr23849920pzg.61.1676131785303; Sat, 11 Feb 2023 08:09:45 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1676131785; cv=none; d=google.com; s=arc-20160816; b=C6eBSODiaGOeAwovmVfH/IPLaW8dq9qWfNQVBlULKRrRFrkm7bKinCg7Glev1xSlbd ecTVhVGP9wSgFhRVIKwp5GgApM+XWx0xLGkRbtFnZscabZfXh/k1mp6cM/7yLNgAAPVB 21yUOyzeVHqv6USavb0Rv7C4dD0hPES9qzrM+SA4j2QcDPMjk+lUGIFpMfcaksy4mqyM hx6LeNYCN7zXleuHb+kELmdGJ462qnu8Os+yZd09WtaeTZYuwEvLzN7xUgquuf+UWCMt IHr7QP0+Jlbg3qwI2LTU0hTVSslydWGRbpZAo8FxavRrggW5X6l7ZeM3kjXzpUdxpYQR EMyw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:in-reply-to:content-transfer-encoding :content-disposition:mime-version:references:message-id:subject:cc :to:from:date; bh=b3J+hmh0/1S38KQRXamDBaq5kS72FcUE3OEFO2SKmYA=; b=JiI6jE9dhyCaM3hpz+IiwtaMDUlArNLHhJUh6oyRcaqS8hfnfrqFnYH5hVmHOk8++N D+vp5ZGkylC5+I3iNFMi64l8af3xIjhh3aDpOOiOXQvLuklwAR+SaPfsDv/ztOBsW+NN W5iP8OtJfVl8BW4iFYwC2upqe1vBpi6MfDRCo1xDX52xrtM1jcxsd/VlIZ3kUoOrn++F BNYDZc3qvlAxzn4CRwIl8UHYF1es58nC+uVKpTPYGyt/K4Cbdkb9EKV2tZhAEjj6N3zq UBH3rVnsYL9rKJUBs+nc9Vs3Pas7iPZAQZc8H5F0kHspZE8H5L7Sv9e6VjwQMpquvGb6 QcqA== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: from out1.vger.email (out1.vger.email. [2620:137:e000::1:20]) by mx.google.com with ESMTP id bg6-20020a17090b0d8600b00233cc2c7da6si835002pjb.79.2023.02.11.08.09.32; Sat, 11 Feb 2023 08:09:45 -0800 (PST) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) client-ip=2620:137:e000::1:20; Authentication-Results: mx.google.com; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S229737AbjBKQFI (ORCPT + 99 others); Sat, 11 Feb 2023 11:05:08 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:50904 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229727AbjBKQFF (ORCPT ); Sat, 11 Feb 2023 11:05:05 -0500 Received: from fudo.makrotopia.org (fudo.makrotopia.org [IPv6:2a07:2ec0:3002::71]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 3547B2BEED; Sat, 11 Feb 2023 08:04:46 -0800 (PST) Received: from local by fudo.makrotopia.org with esmtpsa (TLS1.3:TLS_AES_256_GCM_SHA384:256) (Exim 4.96) (envelope-from ) id 1pQsMm-0004M8-1w; Sat, 11 Feb 2023 17:04:44 +0100 Date: Sat, 11 Feb 2023 16:03:09 +0000 From: Daniel Golle To: netdev@vger.kernel.org, linux-mediatek@lists.infradead.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, Russell King , Heiner Kallweit , Lorenzo Bianconi , Mark Lee , John Crispin , Felix Fietkau , AngeloGioacchino Del Regno , Matthias Brugger , DENG Qingfang , Landen Chao , Sean Wang , Paolo Abeni , Jakub Kicinski , Eric Dumazet , "David S. Miller" , Vladimir Oltean , Florian Fainelli , Andrew Lunn Cc: Jianhui Zhao , =?iso-8859-1?q?Bj=F8rn?= Mork Subject: [PATCH v5 05/12] net: ethernet: mtk_eth_soc: set MDIO bus clock frequency Message-ID: <046e17da34d00d4f545e970272ed6db0afee07eb.1676128246.git.daniel@makrotopia.org> References: MIME-Version: 1.0 Content-Disposition: inline In-Reply-To: X-Spam-Status: No, score=-1.9 required=5.0 tests=BAYES_00,SPF_HELO_NONE, SPF_PASS autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1757551562858465916?= X-GMAIL-MSGID: =?utf-8?q?1757551562858465916?= Set MDIO bus clock frequency and allow setting a custom maximum frequency from device tree. Reviewed-by: Andrew Lunn Reviewed-by: Florian Fainelli Tested-by: Bjørn Mork Signed-off-by: Daniel Golle --- drivers/net/ethernet/mediatek/mtk_eth_soc.c | 21 +++++++++++++++++++++ drivers/net/ethernet/mediatek/mtk_eth_soc.h | 7 +++++++ 2 files changed, 28 insertions(+) diff --git a/drivers/net/ethernet/mediatek/mtk_eth_soc.c b/drivers/net/ethernet/mediatek/mtk_eth_soc.c index cfb15a84b894..030d87c42bd4 100644 --- a/drivers/net/ethernet/mediatek/mtk_eth_soc.c +++ b/drivers/net/ethernet/mediatek/mtk_eth_soc.c @@ -789,8 +789,10 @@ static const struct phylink_mac_ops mtk_phylink_ops = { static int mtk_mdio_init(struct mtk_eth *eth) { + unsigned int max_clk = 2500000, divider; struct device_node *mii_np; int ret; + u32 val; mii_np = of_get_child_by_name(eth->dev->of_node, "mdio-bus"); if (!mii_np) { @@ -818,6 +820,25 @@ static int mtk_mdio_init(struct mtk_eth *eth) eth->mii_bus->parent = eth->dev; snprintf(eth->mii_bus->id, MII_BUS_ID_SIZE, "%pOFn", mii_np); + + if (!of_property_read_u32(mii_np, "clock-frequency", &val)) { + if (val > MDC_MAX_FREQ || val < MDC_MAX_FREQ / MDC_MAX_DIVIDER) { + dev_err(eth->dev, "MDIO clock frequency out of range"); + ret = -EINVAL; + goto err_put_node; + } + max_clk = val; + } + divider = min_t(unsigned int, DIV_ROUND_UP(MDC_MAX_FREQ, max_clk), 63); + + /* Configure MDC Divider */ + val = mtk_r32(eth, MTK_PPSC); + val &= ~PPSC_MDC_CFG; + val |= FIELD_PREP(PPSC_MDC_CFG, divider) | PPSC_MDC_TURBO; + mtk_w32(eth, val, MTK_PPSC); + + dev_dbg(eth->dev, "MDC is running on %d Hz\n", MDC_MAX_FREQ / divider); + ret = of_mdiobus_register(eth->mii_bus, mii_np); err_put_node: diff --git a/drivers/net/ethernet/mediatek/mtk_eth_soc.h b/drivers/net/ethernet/mediatek/mtk_eth_soc.h index 7230dcb29315..7014c02ba2d4 100644 --- a/drivers/net/ethernet/mediatek/mtk_eth_soc.h +++ b/drivers/net/ethernet/mediatek/mtk_eth_soc.h @@ -363,6 +363,13 @@ #define RX_DMA_VTAG_V2 BIT(0) #define RX_DMA_L4_VALID_V2 BIT(2) +/* PHY Polling and SMI Master Control registers */ +#define MTK_PPSC 0x10000 +#define PPSC_MDC_CFG GENMASK(29, 24) +#define PPSC_MDC_TURBO BIT(20) +#define MDC_MAX_FREQ 25000000 +#define MDC_MAX_DIVIDER 63 + /* PHY Indirect Access Control registers */ #define MTK_PHY_IAC 0x10004 #define PHY_IAC_ACCESS BIT(31)