Show patches with: Series = riscv: ASID-related and UP-related TLB flush enhancements       |    Archived = No       |   13 patches
Patch Series A/R/T S/W/F Date Submitter Delegate State
[v5,13/13] riscv: mm: Always use an ASID to flush mm contexts riscv: ASID-related and UP-related TLB flush enhancements - 1 - --- 2024-02-29 Samuel Holland New
[v5,12/13] riscv: mm: Preserve global TLB entries when switching contexts riscv: ASID-related and UP-related TLB flush enhancements - 1 - --- 2024-02-29 Samuel Holland New
[v5,11/13] riscv: mm: Make asid_bits a local variable riscv: ASID-related and UP-related TLB flush enhancements - 1 - --- 2024-02-29 Samuel Holland New
[v5,10/13] riscv: mm: Use a fixed layout for the MM context ID riscv: ASID-related and UP-related TLB flush enhancements - 1 - --- 2024-02-29 Samuel Holland New
[v5,09/13] riscv: mm: Introduce cntx2asid/cntx2version helper macros riscv: ASID-related and UP-related TLB flush enhancements - 1 - --- 2024-02-29 Samuel Holland New
[v5,08/13] riscv: Avoid TLB flush loops when affected by SiFive CIP-1200 riscv: ASID-related and UP-related TLB flush enhancements - - - --- 2024-02-29 Samuel Holland New
[v5,07/13] riscv: Apply SiFive CIP-1200 workaround to single-ASID sfence.vma riscv: ASID-related and UP-related TLB flush enhancements - - - --- 2024-02-29 Samuel Holland New
[v5,06/13] riscv: mm: Combine the SMP and UP TLB flush code riscv: ASID-related and UP-related TLB flush enhancements - 1 - --- 2024-02-29 Samuel Holland New
[v5,05/13] riscv: Only send remote fences when some other CPU is online riscv: ASID-related and UP-related TLB flush enhancements - - - --- 2024-02-29 Samuel Holland New
[v5,04/13] riscv: mm: Broadcast kernel TLB flushes only when needed riscv: ASID-related and UP-related TLB flush enhancements - 1 - --- 2024-02-29 Samuel Holland New
[v5,03/13] riscv: Use IPIs for remote cache/TLB flushes by default riscv: ASID-related and UP-related TLB flush enhancements - - - --- 2024-02-29 Samuel Holland New
[v5,02/13] riscv: Factor out page table TLB synchronization riscv: ASID-related and UP-related TLB flush enhancements - - - --- 2024-02-29 Samuel Holland New
[v5,01/13] riscv: Flush the instruction cache during SMP bringup riscv: ASID-related and UP-related TLB flush enhancements - 1 - --- 2024-02-29 Samuel Holland New