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Introduce Architectural LBR for vPMU
| Archived =
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| 15 patches
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[v2,15/15] KVM: x86/cpuid: Advertise Arch LBR feature in CPUID
Introduce Architectural LBR for vPMU
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2022-11-25
Yang, Weijiang
New
[v2,14/15] KVM: x86: Add Arch LBR data MSR access interface
Introduce Architectural LBR for vPMU
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2022-11-25
Yang, Weijiang
New
[v2,13/15] KVM: x86/vmx: Save/Restore guest Arch LBR Ctrl msr at SMM entry/exit
Introduce Architectural LBR for vPMU
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2022-11-25
Yang, Weijiang
New
[v2,12/15] KVM: x86/vmx: Disable Arch LBREn bit in #DB and warm reset
Introduce Architectural LBR for vPMU
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2022-11-25
Yang, Weijiang
New
[v2,11/15] KVM: x86: Add XSAVE Support for Architectural LBR
Introduce Architectural LBR for vPMU
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2022-11-25
Yang, Weijiang
New
[v2,10/15] KVM: x86/vmx: Check Arch LBR config when return perf capabilities
Introduce Architectural LBR for vPMU
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2022-11-25
Yang, Weijiang
New
[v2,09/15] KVM: x86: Refine the matching and clearing logic for supported_xss
Introduce Architectural LBR for vPMU
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2022-11-25
Yang, Weijiang
New
[v2,08/15] KVM: x86: Add Arch LBR MSRs to msrs_to_save_all list
Introduce Architectural LBR for vPMU
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2022-11-25
Yang, Weijiang
New
[v2,07/15] KVM: VMX: Support passthrough of architectural LBRs
Introduce Architectural LBR for vPMU
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2022-11-25
Yang, Weijiang
New
[v2,06/15] KVM: vmx/pmu: Emulate MSR_ARCH_LBR_CTL for guest Arch LBR
Introduce Architectural LBR for vPMU
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2022-11-25
Yang, Weijiang
New
[v2,05/15] KVM: vmx/pmu: Emulate MSR_ARCH_LBR_DEPTH for guest Arch LBR
Introduce Architectural LBR for vPMU
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2022-11-25
Yang, Weijiang
New
[v2,04/15] KVM: PMU: disable LBR handling if architectural LBR is available
Introduce Architectural LBR for vPMU
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2022-11-25
Yang, Weijiang
New
[v2,03/15] KVM: x86: Refresh CPUID on writes to MSR_IA32_XSS
Introduce Architectural LBR for vPMU
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2022-11-25
Yang, Weijiang
New
[v2,02/15] KVM: x86: Report XSS as an MSR to be saved if there are supported features
Introduce Architectural LBR for vPMU
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2022-11-25
Yang, Weijiang
New
[v2,01/15] perf/x86/lbr: Simplify the exposure check for the LBR_INFO registers
Introduce Architectural LBR for vPMU
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2022-11-25
Yang, Weijiang
New