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Show patches with
: Submitter =
Clément Léger
| State =
Action Required
| Archived =
No
| 153 patches
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Patch
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S/W/F
Date
Submitter
Delegate
State
[v1,12/13] riscv: hwprobe: export Zvfh[min] ISA extensions
riscv: report more ISA extensions through hwprobe
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2023-10-11
Clément Léger
New
[v1,11/13] riscv: add ISA extension probing for Zvfh[min]
riscv: report more ISA extensions through hwprobe
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2023-10-11
Clément Léger
New
[v1,10/13] dt-bindings: riscv: add Zihintntl ISA extension description
riscv: report more ISA extensions through hwprobe
1 - -
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2023-10-11
Clément Léger
New
[v1,09/13] riscv: hwprobe: export Zhintntl ISA extension
riscv: report more ISA extensions through hwprobe
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2023-10-11
Clément Léger
New
[v1,08/13] riscv: add ISA extension probing for Zihintntl
riscv: report more ISA extensions through hwprobe
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2023-10-11
Clément Léger
New
[v1,07/13] dt-bindings: riscv: add Zfh/Zfhmin ISA extensions description
riscv: report more ISA extensions through hwprobe
1 - -
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2023-10-11
Clément Léger
New
[v1,06/13] riscv: hwprobe: export Zfh/Zfhmin ISA extensions
riscv: report more ISA extensions through hwprobe
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2023-10-11
Clément Léger
New
[v1,05/13] riscv: add ISA extension probing for Zfh/Zfhmin
riscv: report more ISA extensions through hwprobe
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2023-10-11
Clément Léger
New
[v1,04/13] dt-bindings: riscv: add Zv* ratified crypto ISA extensions description
riscv: report more ISA extensions through hwprobe
1 - -
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2023-10-11
Clément Léger
New
[v1,03/13] riscv: hwprobe: export Zv* ISA extensions
riscv: report more ISA extensions through hwprobe
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2023-10-11
Clément Léger
New
[v1,02/13] riscv: add ISA extension probing for Zv* extensions
riscv: report more ISA extensions through hwprobe
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2023-10-11
Clément Léger
New
[v1,01/13] riscv: fatorize hwprobe ISA extension reporting
riscv: report more ISA extensions through hwprobe
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2023-10-11
Clément Léger
New
[v2,8/8] riscv: add support for PR_SET_UNALIGN and PR_GET_UNALIGN
Add support to handle misaligned accesses in S-mode
- 1 -
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2023-10-04
Clément Léger
New
[v2,7/8] riscv: report misaligned accesses emulation to hwprobe
Add support to handle misaligned accesses in S-mode
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2023-10-04
Clément Léger
New
[v2,6/8] riscv: annotate check_unaligned_access_boot_cpu() with __init
Add support to handle misaligned accesses in S-mode
- 1 -
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2023-10-04
Clément Léger
New
[v2,5/8] riscv: add support for sysctl unaligned_enabled control
Add support to handle misaligned accesses in S-mode
- 1 -
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2023-10-04
Clément Léger
New
[v2,4/8] riscv: add floating point insn support to misaligned access emulation
Add support to handle misaligned accesses in S-mode
- - -
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2023-10-04
Clément Léger
New
[v2,3/8] riscv: report perf event for misaligned fault
Add support to handle misaligned accesses in S-mode
- 1 -
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2023-10-04
Clément Léger
New
[v2,2/8] riscv: add support for misaligned trap handling in S-mode
Add support to handle misaligned accesses in S-mode
- 1 -
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2023-10-04
Clément Léger
New
[v2,1/8] riscv: remove unused functions in traps_misaligned.c
Add support to handle misaligned accesses in S-mode
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2023-10-04
Clément Léger
New
[5/5] riscv: kvm: use ".L" local labels in assembly when applicable
riscv: cleanup assembly usage of ENTRY()/END() and use local labels
- 1 -
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2023-10-04
Clément Léger
New
[4/5] riscv: kvm: Use SYM_*() assembly macros instead of deprecated ones
riscv: cleanup assembly usage of ENTRY()/END() and use local labels
- 1 -
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2023-10-04
Clément Léger
New
[3/5] riscv: kernel: Use correct SYM_DATA_*() macro for data
riscv: cleanup assembly usage of ENTRY()/END() and use local labels
- 1 -
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2023-10-04
Clément Léger
New
[2/5] riscv: Use SYM_*() assembly macros instead of deprecated ones
riscv: cleanup assembly usage of ENTRY()/END() and use local labels
- - -
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2023-10-04
Clément Léger
New
[1/5] riscv: use ".L" local labels in assembly when applicable
riscv: cleanup assembly usage of ENTRY()/END() and use local labels
- 1 -
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2023-10-04
Clément Léger
New
riscv: blacklist assembly symbols for kprobe
riscv: blacklist assembly symbols for kprobe
- 1 -
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2023-10-04
Clément Léger
New
[v2] tracing: relax trace_event_eval_update() execution with cond_resched()
[v2] tracing: relax trace_event_eval_update() execution with cond_resched()
- 1 1
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2023-09-29
Clément Léger
New
tracing: relax trace_event_eval_update() execution with schedule()
tracing: relax trace_event_eval_update() execution with schedule()
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2023-09-29
Clément Léger
New
[7/7] riscv: add support for PR_SET_UNALIGN and PR_GET_UNALIGN
Add support to handle misaligned accesses in S-mode
- - -
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2023-09-26
Clément Léger
New
[6/7] riscv: report misaligned accesses emulation to hwprobe
Add support to handle misaligned accesses in S-mode
- - -
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2023-09-26
Clément Léger
New
[5/7] riscv: add support for sysctl unaligned_enabled control
Add support to handle misaligned accesses in S-mode
- - -
-
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2023-09-26
Clément Léger
New
[4/7] riscv: add floating point insn support to misaligned access emulation
Add support to handle misaligned accesses in S-mode
- - -
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2023-09-26
Clément Léger
New
[3/7] riscv: report perf event for misaligned fault
Add support to handle misaligned accesses in S-mode
- - -
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2023-09-26
Clément Léger
New
[2/7] riscv: add support for misaligned handling in S-mode
Add support to handle misaligned accesses in S-mode
- - -
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2023-09-26
Clément Léger
New
[1/7] riscv: remove unused functions in traps_misaligned.c
Add support to handle misaligned accesses in S-mode
- - -
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2023-09-26
Clément Léger
New
tracing/user_events: align uaddr on unsigned long alignment
tracing/user_events: align uaddr on unsigned long alignment
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2023-09-14
Clément Léger
New
selftests: sud_test: return correct emulated syscall value on RISC-V
selftests: sud_test: return correct emulated syscall value on RISC-V
1 1 -
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2023-09-13
Clément Léger
New
scripts/gdb: fix usage of MOD_TEXT not defined when CONFIG_MODULES=n
scripts/gdb: fix usage of MOD_TEXT not defined when CONFIG_MODULES=n
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2023-08-01
Clément Léger
New
[RFC,V2,9/9] riscv: add floating point insn support to misaligned access emulation
Add support to handle misaligned accesses in S-mode
- - -
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2023-07-04
Clément Léger
New
[RFC,V2,8/9] riscv: add support for PR_SET_UNALIGN and PR_GET_UNALIGN
Add support to handle misaligned accesses in S-mode
- - -
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2023-07-04
Clément Léger
New
[RFC,V2,7/9] riscv: report misaligned accesses emulation to hwprobe
Add support to handle misaligned accesses in S-mode
- - -
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2023-07-04
Clément Léger
New
[RFC,V2,6/9] riscv: add support for SBI misalignment trap delegation
Add support to handle misaligned accesses in S-mode
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2023-07-04
Clément Léger
New
[RFC,V2,5/9] riscv: add support for sysctl unaligned_enabled control
Add support to handle misaligned accesses in S-mode
- - -
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2023-07-04
Clément Léger
New
[RFC,V2,4/9] riscv: report perf event for misaligned fault
Add support to handle misaligned accesses in S-mode
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2023-07-04
Clément Léger
New
[RFC,V2,3/9] riscv: add support for misaligned handling in S-mode
Add support to handle misaligned accesses in S-mode
- - -
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2023-07-04
Clément Léger
New
[RFC,V2,2/9] riscv: avoid missing prototypes warning
Add support to handle misaligned accesses in S-mode
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2023-07-04
Clément Léger
New
[RFC,V2,1/9] riscv: remove unused functions in traps_misaligned.c
Add support to handle misaligned accesses in S-mode
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2023-07-04
Clément Léger
New
[RFC,6/6] riscv: add floating point insn support to misaligned access emulation
Add support to handle misaligned accesses in S-mode
- - -
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2023-06-24
Clément Léger
New
[RFC,5/6] riscv: add support for PR_SET_UNALIGN and PR_GET_UNALIGN
Add support to handle misaligned accesses in S-mode
- - -
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2023-06-24
Clément Léger
New
[RFC,4/6] riscv: add support for SBI misalignment trap delegation
Add support to handle misaligned accesses in S-mode
- - -
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2023-06-24
Clément Léger
New
[RFC,3/6] riscv: allow S-mode to handle misaligned traps
Add support to handle misaligned accesses in S-mode
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2023-06-24
Clément Léger
New
[RFC,2/6] riscv: add support for misaligned handling in S-mode
Add support to handle misaligned accesses in S-mode
- - -
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2023-06-24
Clément Léger
New
[RFC,1/6] riscv: remove unused functions in traps_misaligned.c
Add support to handle misaligned accesses in S-mode
- - -
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2023-06-24
Clément Léger
New
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