Show patches with: Submitter = Havalige, Thippeswamy       |   62 patches
Patch Series A/R/T S/W/F Date Submitter Delegate State
[v5,RESEND,4/4] PCI: xilinx-nwl: Increase ECAM size to accommodate 256 buses increase ecam size value to discover 256 buses during - - - --- 2023-10-16 Havalige, Thippeswamy New
[v5,RESEND,3/4] PCI: xilinx-nwl: Rename ECAM size default macro increase ecam size value to discover 256 buses during - - - --- 2023-10-16 Havalige, Thippeswamy New
[v5,RESEND,2/4] dt-bindings: PCI: xilinx-nwl: Modify ECAM size in example increase ecam size value to discover 256 buses during 1 - - --- 2023-10-16 Havalige, Thippeswamy New
[v5,RESEND,1/4] PCI: xilinx-nwl: Remove unnecessary code which updates primary, secondary and sub-o… increase ecam size value to discover 256 buses during - - - --- 2023-10-16 Havalige, Thippeswamy New
[v5,RESEND,4/4] PCI: xilinx-nwl: Increase ECAM size to accommodate 256 buses ncrease ecam size value to discover 256 buses during - - - --- 2023-10-05 Havalige, Thippeswamy New
[v5,RESEND,3/4] PCI: xilinx-nwl: Rename ECAM size default macro ncrease ecam size value to discover 256 buses during - - - --- 2023-10-05 Havalige, Thippeswamy New
[v5,RESEND,2/4] dt-bindings: PCI: xilinx-nwl: Modify ECAM size in example ncrease ecam size value to discover 256 buses during 1 - - --- 2023-10-05 Havalige, Thippeswamy New
[v5,RESEND,1/4] PCI: xilinx-nwl: Remove unnecessary code which updates primary, secondary and sub-o… ncrease ecam size value to discover 256 buses during - - - --- 2023-10-05 Havalige, Thippeswamy New
[v7,RESEND,3/3] PCI: xilinx-xdma: Add Xilinx XDMA Root Port driver Add support for Xilinx XDMA Soft IP as Root Port. - - - --- 2023-10-03 Havalige, Thippeswamy New
[v7,RESEND,2/3] dt-bindings: PCI: xilinx-xdma: Add YAML schemas for Xilinx XDMA PCIe Root Port Brid… Add support for Xilinx XDMA Soft IP as Root Port. 1 1 - --- 2023-10-03 Havalige, Thippeswamy New
[v7,RESEND,1/3] PCI: xilinx-cpm: Move interrupt bit definitions to common header Add support for Xilinx XDMA Soft IP as Root Port. - - - --- 2023-10-03 Havalige, Thippeswamy New
[v4,2/3] PCI: xilinx-nwl: Rename ECAM size default macro. [v4,1/3] dt-bindings: PCI: xilinx-nwl: Modify ECAM size in example - - - --- 2023-08-14 Havalige, Thippeswamy New
[v4,1/3] dt-bindings: PCI: xilinx-nwl: Modify ECAM size in example [v4,1/3] dt-bindings: PCI: xilinx-nwl: Modify ECAM size in example 1 - - --- 2023-08-14 Havalige, Thippeswamy New
[v3,2/2] PCI: xilinx-nwl: Increase ECAM size to accommodate 256 buses [v3] PCI: xilinx-nwl: Remove unnecessary code which updates primary, secondary and sub-ordinate bus… - - - --- 2023-08-10 Havalige, Thippeswamy New
[v3,1/2] dt-bindings: PCI: xilinx-nwl: Modify ECAM size in example [v3,1/2] dt-bindings: PCI: xilinx-nwl: Modify ECAM size in example 1 - - --- 2023-08-10 Havalige, Thippeswamy New
[v3] PCI: xilinx-nwl: Remove unnecessary code which updates primary, secondary and sub-ordinate bus… [v3] PCI: xilinx-nwl: Remove unnecessary code which updates primary, secondary and sub-ordinate bus… - - - --- 2023-08-10 Havalige, Thippeswamy New
[v2,2/2] PCI: xilinx-nwl: Increase ECAM size to accommodate 256 buses. [v2,1/2] dt-bindings: PCI: xilinx-nwl: Modify ECAM size in example. - - - --- 2023-08-08 Havalige, Thippeswamy New
[v2,1/2] dt-bindings: PCI: xilinx-nwl: Modify ECAM size in example. [v2,1/2] dt-bindings: PCI: xilinx-nwl: Modify ECAM size in example. - - - --- 2023-08-08 Havalige, Thippeswamy New
[v2] PCI: xilinx-nwl: Remove unnecessary code which updates primary,secondary and sub-ordinate bus … [v2] PCI: xilinx-nwl: Remove unnecessary code which updates primary,secondary and sub-ordinate bus … - - - --- 2023-08-08 Havalige, Thippeswamy New
[v1,2/2] dt-bindings: PCI: xilinx-nwl: Modify ECAM size in example. Fix ecam size value to discover 256 buses during - - - --- 2023-08-07 Havalige, Thippeswamy New
[v1,1/2] PCI: xilinx-nwl: Update ECAM default value and remove unnecessary code. Fix ecam size value to discover 256 buses during - - - --- 2023-08-07 Havalige, Thippeswamy New
[v1,1/2] PCI: xilinx-nwl: Update ECAM default value and remove unnecessary code. Fix ecam size value to discover 256 buses during - - - --- 2023-08-07 Havalige, Thippeswamy New
PCI: xilinx-nwl: Remove unnecessary code and updating ecam default value. PCI: xilinx-nwl: Remove unnecessary code and updating ecam default value. - - - --- 2023-08-03 Havalige, Thippeswamy New
[V5,3/3] PCI: xilinx-xdma: Add Xilinx XDMA Root Port driver Add support for Xilinx XDMA Soft IP as Root Port. - - - --- 2023-06-28 Havalige, Thippeswamy New
[V5,2/3] dt-bindings: PCI: xilinx-xdma: Add YAML schemas for Xilinx XDMA PCIe Root Port Bridge Add support for Xilinx XDMA Soft IP as Root Port. 1 1 - --- 2023-06-28 Havalige, Thippeswamy New
[V5,1/3] Move and rename error interrupt bits to a common header. Add support for Xilinx XDMA Soft IP as Root Port. - - - --- 2023-06-28 Havalige, Thippeswamy New
[v4,3/3] PCI: xilinx-xdma: Add Xilinx XDMA Root Port driver Add support for Xilinx XDMA Soft IP as Root Port. - - - --- 2023-05-31 Havalige, Thippeswamy New
[v4,2/3] dt-bindings: PCI: xilinx-xdma: Add YAML schemas for Xilinx XDMA PCIe Root Port Bridge Add support for Xilinx XDMA Soft IP as Root Port. - 1 - --- 2023-05-31 Havalige, Thippeswamy New
[v4,1/3] Move and rename error interrupt bits to a common header. Add support for Xilinx XDMA Soft IP as Root Port. - - - --- 2023-05-31 Havalige, Thippeswamy New
[v3,3/3] PCI: xilinx-xdma: Add Xilinx XDMA Root Port driver Add support for Xilinx XDMA Soft IP as Root Port. - - - --- 2023-05-19 Havalige, Thippeswamy New
[v3,2/3] dt-bindings: PCI: xilinx-xdma: Add YAML schemas for Xilinx XDMA PCIe Root Port Bridge Add support for Xilinx XDMA Soft IP as Root Port. - - - --- 2023-05-19 Havalige, Thippeswamy New
[v3,1/3] Move and rename error interrupt bits to a common header. Add support for Xilinx XDMA Soft IP as Root Port. - - - --- 2023-05-19 Havalige, Thippeswamy New
[v2,3/3] PCI: xilinx-xdma: Add Xilinx XDMA Root Port driver Add support for Xilinx XDMA Soft IP as Root Port. - - - --- 2023-05-12 Havalige, Thippeswamy New
[v2,2/3] dt-bindings: PCI: xilinx-xdma: Add YAML schemas for Xilinx XDMA PCIe Root Port Bridge Add support for Xilinx XDMA Soft IP as Root Port. - - - --- 2023-05-12 Havalige, Thippeswamy New
[v2,1/3] Move error interrupt bits to a common header. Add support for Xilinx XDMA Soft IP as Root Port. - - - --- 2023-05-12 Havalige, Thippeswamy New
[2/2] PCI: xilinx-xdma: Add Xilinx XDMA Root Port driver Add support for Xilinx XDMA Soft IP as Root Port. - - - --- 2023-04-17 Havalige, Thippeswamy New
[1/2] dt-bindings: PCI: xilinx-xdma: Add YAML schemas for Xilinx XDMA PCIe Root Port Bridge Add support for Xilinx XDMA Soft IP as Root Port. - - - --- 2023-04-17 Havalige, Thippeswamy New
[v6,2/2] dt-bindings: PCI: xilinx-nwl: Convert to YAML schemas of Xilinx NWL PCIe Root Port Bridge [v6,1/2] dt-bindings: PCI: xilinx-pcie: Convert to YAML schemas of Xilinx AXI PCIe Root Port Bridge - 1 - --- 2022-11-11 Havalige, Thippeswamy New
[v6,1/2] dt-bindings: PCI: xilinx-pcie: Convert to YAML schemas of Xilinx AXI PCIe Root Port Bridge [v6,1/2] dt-bindings: PCI: xilinx-pcie: Convert to YAML schemas of Xilinx AXI PCIe Root Port Bridge - 1 - --- 2022-11-11 Havalige, Thippeswamy New
[v5,2/2] dt-bindings: PCI: xilinx-nwl: Convert to YAML schemas of Xilinx NWL PCIe Root Port Bridge [v5,1/2] dt-bindings: PCI: xilinx-pcie: Convert to YAML schemas of Xilinx AXI PCIe Root Port Bridge - - - --- 2022-11-08 Havalige, Thippeswamy New
[v5,1/2] dt-bindings: PCI: xilinx-pcie: Convert to YAML schemas of Xilinx AXI PCIe Root Port Bridge [v5,1/2] dt-bindings: PCI: xilinx-pcie: Convert to YAML schemas of Xilinx AXI PCIe Root Port Bridge - 1 - --- 2022-11-08 Havalige, Thippeswamy New
[v4,2/2] dt-bindings: PCI: xilinx-nwl: Convert to YAML schemas of Xilinx NWL PCIe Root Port Bridge [v4,1/2] dt-bindings: PCI: xilinx-pcie: Convert to YAML schemas of Xilinx AXI PCIe Root Port Bridge - - - --- 2022-11-07 Havalige, Thippeswamy New
[v4,1/2] dt-bindings: PCI: xilinx-pcie: Convert to YAML schemas of Xilinx AXI PCIe Root Port Bridge [v4,1/2] dt-bindings: PCI: xilinx-pcie: Convert to YAML schemas of Xilinx AXI PCIe Root Port Bridge - 1 - --- 2022-11-07 Havalige, Thippeswamy New
[v3,2/2] dt-bindings: PCI: xilinx-nwl: Convert to YAML schemas of Xilinx NWL PCIe Root Port Bridge [v3,1/2] dt-bindings: PCI: xilinx-pcie: Convert to YAML schemas of Xilinx AXI PCIe Root Port Bridge - - - --- 2022-11-04 Havalige, Thippeswamy New
[v3,1/2] dt-bindings: PCI: xilinx-pcie: Convert to YAML schemas of Xilinx AXI PCIe Root Port Bridge [v3,1/2] dt-bindings: PCI: xilinx-pcie: Convert to YAML schemas of Xilinx AXI PCIe Root Port Bridge - - - --- 2022-11-04 Havalige, Thippeswamy New
[v2,2/2] dt-bindings: PCI: xilinx-nwl: Convert to YAML schemas of Xilinx NWL PCIe Root Port Bridge [v2,1/2] dt-bindings: PCI: xilinx-pcie: Convert to YAML schemas of Xilinx AXI PCIe Root Port Bridge - - - --- 2022-11-01 Havalige, Thippeswamy New
[v2,1/2] dt-bindings: PCI: xilinx-pcie: Convert to YAML schemas of Xilinx AXI PCIe Root Port Bridge [v2,1/2] dt-bindings: PCI: xilinx-pcie: Convert to YAML schemas of Xilinx AXI PCIe Root Port Bridge - - - --- 2022-11-01 Havalige, Thippeswamy New
[13/13] microblaze/PCI: Moving PCI iounmap and dependent code Remove unused microblaze PCIe bus architecture - - - --- 2022-10-25 Havalige, Thippeswamy New
[12/13] microblaze/PCI: Remove support for Xilinx PCI host bridge Remove unused microblaze PCIe bus architecture - - - --- 2022-10-25 Havalige, Thippeswamy New
[11/13] microblaze/PCI: Remove unused pci_iobar_pfn() and et al declarations Remove unused microblaze PCIe bus architecture - - - --- 2022-10-25 Havalige, Thippeswamy New
[10/13] microblaze/PCI: Remove unused sys_pciconfig_iobase() and et al declaration Remove unused microblaze PCIe bus architecture - - - --- 2022-10-25 Havalige, Thippeswamy New
[09/13] microblaze/PCI: Remove unused pci_address_to_pio() conversion of CPU address to I/O port Remove unused microblaze PCIe bus architecture - - - --- 2022-10-25 Havalige, Thippeswamy New
[08/13] microblaze/PCI: Remove unused PCI Indirect ops Remove unused microblaze PCIe bus architecture - - - --- 2022-10-25 Havalige, Thippeswamy New
[07/13] microblaze/PCI: Remove unused PCI BIOS resource allocation Remove unused microblaze PCIe bus architecture - - - --- 2022-10-25 Havalige, Thippeswamy New
[06/13] microblaze/PCI: Remove unused allocation & free of PCI host bridge structure Remove unused microblaze PCIe bus architecture - - - --- 2022-10-25 Havalige, Thippeswamy New
[05/13] microblaze/PCI: Remove unused device tree parsing for a host bridge resources Remove unused microblaze PCIe bus architecture - - - --- 2022-10-25 Havalige, Thippeswamy New
[04/13] microblaze/PCI: Remove unused PCI legacy IO's access on a bus Remove unused microblaze PCIe bus architecture - - - --- 2022-10-25 Havalige, Thippeswamy New
[03/13] microblaze/PCI: Remove unused PCI bus scan if configured as a host Remove unused microblaze PCIe bus architecture - - - --- 2022-10-25 Havalige, Thippeswamy New
[02/13] microblaze/PCI: Remove Null PCI config access unused functions Remove unused microblaze PCIe bus architecture - - - --- 2022-10-25 Havalige, Thippeswamy New
[01/13] microblaze/PCI: Remove unused early_read_config_byte() et al declarations Remove unused microblaze PCIe bus architecture - - - --- 2022-10-25 Havalige, Thippeswamy New
[2/2] dt-bindings: PCI: xilinx-nwl: Convert to YAML schemas of Xilinx NWL PCIe Root Port Bridge [1/2] dt-bindings: PCI: xilinx-pcie: Convert to YAML schemas of Xilinx AXI PCIe Root Port Bridge - - - --- 2022-10-19 Havalige, Thippeswamy New
[1/2] dt-bindings: PCI: xilinx-pcie: Convert to YAML schemas of Xilinx AXI PCIe Root Port Bridge [1/2] dt-bindings: PCI: xilinx-pcie: Convert to YAML schemas of Xilinx AXI PCIe Root Port Bridge - - - --- 2022-10-19 Havalige, Thippeswamy New