Show patches with: Submitter = Samuel Holland       |   139 patches
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Patch Series A/R/T S/W/F Date Submitter Delegate State
riscv: mm: Fix prototype to avoid discarding const riscv: mm: Fix prototype to avoid discarding const - 1 - --- 2024-03-01 Samuel Holland New
[v5,13/13] riscv: mm: Always use an ASID to flush mm contexts riscv: ASID-related and UP-related TLB flush enhancements - 1 - --- 2024-02-29 Samuel Holland New
[v5,12/13] riscv: mm: Preserve global TLB entries when switching contexts riscv: ASID-related and UP-related TLB flush enhancements - 1 - --- 2024-02-29 Samuel Holland New
[v5,11/13] riscv: mm: Make asid_bits a local variable riscv: ASID-related and UP-related TLB flush enhancements - 1 - --- 2024-02-29 Samuel Holland New
[v5,10/13] riscv: mm: Use a fixed layout for the MM context ID riscv: ASID-related and UP-related TLB flush enhancements - 1 - --- 2024-02-29 Samuel Holland New
[v5,09/13] riscv: mm: Introduce cntx2asid/cntx2version helper macros riscv: ASID-related and UP-related TLB flush enhancements - 1 - --- 2024-02-29 Samuel Holland New
[v5,08/13] riscv: Avoid TLB flush loops when affected by SiFive CIP-1200 riscv: ASID-related and UP-related TLB flush enhancements - - - --- 2024-02-29 Samuel Holland New
[v5,07/13] riscv: Apply SiFive CIP-1200 workaround to single-ASID sfence.vma riscv: ASID-related and UP-related TLB flush enhancements - - - --- 2024-02-29 Samuel Holland New
[v5,06/13] riscv: mm: Combine the SMP and UP TLB flush code riscv: ASID-related and UP-related TLB flush enhancements - 1 - --- 2024-02-29 Samuel Holland New
[v5,05/13] riscv: Only send remote fences when some other CPU is online riscv: ASID-related and UP-related TLB flush enhancements - - - --- 2024-02-29 Samuel Holland New
[v5,04/13] riscv: mm: Broadcast kernel TLB flushes only when needed riscv: ASID-related and UP-related TLB flush enhancements - 1 - --- 2024-02-29 Samuel Holland New
[v5,03/13] riscv: Use IPIs for remote cache/TLB flushes by default riscv: ASID-related and UP-related TLB flush enhancements - - - --- 2024-02-29 Samuel Holland New
[v5,02/13] riscv: Factor out page table TLB synchronization riscv: ASID-related and UP-related TLB flush enhancements - - - --- 2024-02-29 Samuel Holland New
[v5,01/13] riscv: Flush the instruction cache during SMP bringup riscv: ASID-related and UP-related TLB flush enhancements - 1 - --- 2024-02-29 Samuel Holland New
[-fixes,v4,3/3] riscv: Save/restore envcfg CSR during CPU suspend riscv: cbo.zero fixes - 2 - --- 2024-02-28 Samuel Holland New
[-fixes,v4,2/3] riscv: Add a custom ISA extension for the [ms]envcfg CSR riscv: cbo.zero fixes - 2 - --- 2024-02-28 Samuel Holland New
[-fixes,v4,1/3] riscv: Fix enabling cbo.zero when running in M-mode riscv: cbo.zero fixes - 2 - --- 2024-02-28 Samuel Holland New
[4/4] riscv: Allow NOMMU kernels to run in S-mode riscv: 64-bit NOMMU fixes and enhancements - 1 - --- 2024-02-27 Samuel Holland New
[3/4] riscv: Remove MMU dependency from Zbb and Zicboz riscv: 64-bit NOMMU fixes and enhancements - 1 - --- 2024-02-27 Samuel Holland New
[2/4] riscv: Fix loading 64-bit NOMMU kernels past the start of RAM riscv: 64-bit NOMMU fixes and enhancements - - - --- 2024-02-27 Samuel Holland New
[1/4] riscv: Fix TASK_SIZE on 64-bit NOMMU riscv: 64-bit NOMMU fixes and enhancements - - - --- 2024-02-27 Samuel Holland New
[v1,6/6] drivers/perf: Add SiFive Private L2 Cache PMU driver SiFive cache controller PMU drivers - - - --- 2024-02-16 Samuel Holland New
[v1,5/6] dt-bindings: cache: Add SiFive Private L2 Cache controller SiFive cache controller PMU drivers - - - --- 2024-02-16 Samuel Holland New
[v1,4/6] drivers/perf: Add SiFive Extensible Cache PMU driver SiFive cache controller PMU drivers - - - --- 2024-02-16 Samuel Holland New
[v1,3/6] dt-bindings: cache: Add SiFive Extensible Cache controller SiFive cache controller PMU drivers - - - --- 2024-02-16 Samuel Holland New
[v1,2/6] drivers/perf: Add SiFive Composable Cache PMU driver SiFive cache controller PMU drivers - - - --- 2024-02-16 Samuel Holland New
[v1,1/6] dt-bindings: cache: Document the sifive,perfmon-counters property SiFive cache controller PMU drivers - - - --- 2024-02-16 Samuel Holland New
MAINTAINERS: Update SiFive driver maintainers MAINTAINERS: Update SiFive driver maintainers 3 - - --- 2024-02-15 Samuel Holland New
[-fixes,v3,2/2] riscv: Save/restore envcfg CSR during CPU suspend riscv: cbo.zero fixes - 1 - --- 2024-02-14 Samuel Holland New
[-fixes,v3,1/2] riscv: Fix enabling cbo.zero when running in M-mode riscv: cbo.zero fixes - 1 - --- 2024-02-14 Samuel Holland New
[-fixes,v2,4/4] riscv: Save/restore envcfg CSR during CPU suspend riscv: cbo.zero fixes - - - --- 2024-02-13 Samuel Holland New
[-fixes,v2,3/4] riscv: Add ISA extension parsing for Sm and Ss riscv: cbo.zero fixes - - - --- 2024-02-13 Samuel Holland New
[-fixes,v2,2/4] dt-bindings: riscv: Add ratified privileged ISA versions riscv: cbo.zero fixes - 1 - --- 2024-02-13 Samuel Holland New
[-fixes,v2,1/4] riscv: Fix enabling cbo.zero when running in M-mode riscv: cbo.zero fixes - 1 - --- 2024-02-13 Samuel Holland New
[7/7] riscv: Remove extra variable in patch_text_nosync() riscv: Various text patching improvements - 1 - --- 2024-02-12 Samuel Holland New
[6/7] riscv: Use offset_in_page() in text patching functions riscv: Various text patching improvements - 1 - --- 2024-02-12 Samuel Holland New
[5/7] riscv: Pass patch_text() the length in bytes riscv: Various text patching improvements - 1 - --- 2024-02-12 Samuel Holland New
[4/7] riscv: Simplify text patching loops riscv: Various text patching improvements - - - --- 2024-02-12 Samuel Holland New
[3/7] riscv: kprobes: Use patch_text_nosync() for insn slots riscv: Various text patching improvements - 1 - --- 2024-02-12 Samuel Holland New
[2/7] riscv: jump_label: Simplify assembly syntax riscv: Various text patching improvements - 1 - --- 2024-02-12 Samuel Holland New
[1/7] riscv: jump_label: Batch icache maintenance riscv: Various text patching improvements - 1 - --- 2024-02-12 Samuel Holland New
[-fixes,2/2] riscv: Save/restore envcfg CSR during CPU suspend [-fixes,1/2] riscv: Fix enabling cbo.zero when running in M-mode - 1 - --- 2024-02-12 Samuel Holland New
[-fixes,1/2] riscv: Fix enabling cbo.zero when running in M-mode [-fixes,1/2] riscv: Fix enabling cbo.zero when running in M-mode - 1 - --- 2024-02-12 Samuel Holland New
scs: add CONFIG_MMU dependency for vfree_atomic() scs: add CONFIG_MMU dependency for vfree_atomic() - 1 - --- 2024-01-22 Samuel Holland New
perf: RISC-V: Check standard event availability perf: RISC-V: Check standard event availability - - - --- 2024-01-03 Samuel Holland New
[v4,12/12] riscv: mm: Always use an ASID to flush mm contexts riscv: ASID-related and UP-related TLB flush enhancements - 1 - --- 2024-01-02 Samuel Holland New
[v4,11/12] riscv: mm: Preserve global TLB entries when switching contexts riscv: ASID-related and UP-related TLB flush enhancements - 1 - --- 2024-01-02 Samuel Holland New
[v4,10/12] riscv: mm: Make asid_bits a local variable riscv: ASID-related and UP-related TLB flush enhancements - 1 - --- 2024-01-02 Samuel Holland New
[v4,09/12] riscv: mm: Use a fixed layout for the MM context ID riscv: ASID-related and UP-related TLB flush enhancements - 1 - --- 2024-01-02 Samuel Holland New
[v4,08/12] riscv: mm: Introduce cntx2asid/cntx2version helper macros riscv: ASID-related and UP-related TLB flush enhancements - 1 - --- 2024-01-02 Samuel Holland New
[v4,07/12] riscv: Avoid TLB flush loops when affected by SiFive CIP-1200 riscv: ASID-related and UP-related TLB flush enhancements - - - --- 2024-01-02 Samuel Holland New
[v4,06/12] riscv: Apply SiFive CIP-1200 workaround to single-ASID sfence.vma riscv: ASID-related and UP-related TLB flush enhancements - - - --- 2024-01-02 Samuel Holland New
[v4,05/12] riscv: mm: Combine the SMP and UP TLB flush code riscv: ASID-related and UP-related TLB flush enhancements - 1 - --- 2024-01-02 Samuel Holland New
[v4,04/12] riscv: Only send remote fences when some other CPU is online riscv: ASID-related and UP-related TLB flush enhancements - - - --- 2024-01-02 Samuel Holland New
[v4,03/12] riscv: mm: Broadcast kernel TLB flushes only when needed riscv: ASID-related and UP-related TLB flush enhancements - 1 - --- 2024-01-02 Samuel Holland New
[v4,02/12] riscv: Use IPIs for remote cache/TLB flushes by default riscv: ASID-related and UP-related TLB flush enhancements - 1 - --- 2024-01-02 Samuel Holland New
[v4,01/12] riscv: Flush the instruction cache during SMP bringup riscv: ASID-related and UP-related TLB flush enhancements - 1 - --- 2024-01-02 Samuel Holland New
[v2,14/14] selftests/fpu: Allow building on other architectures Unified cross-architecture kernel-mode FPU API - 1 - --- 2023-12-28 Samuel Holland New
[v2,13/14] selftests/fpu: Move FP code to a separate translation unit Unified cross-architecture kernel-mode FPU API - 1 - --- 2023-12-28 Samuel Holland New
[v2,12/14] drm/amd/display: Use ARCH_HAS_KERNEL_FPU_SUPPORT Unified cross-architecture kernel-mode FPU API - - - --- 2023-12-28 Samuel Holland New
[v2,11/14] drm/amd/display: Only use hard-float, not altivec on powerpc Unified cross-architecture kernel-mode FPU API - - - --- 2023-12-28 Samuel Holland New
[v2,10/14] riscv: Add support for kernel-mode FPU Unified cross-architecture kernel-mode FPU API 1 2 - --- 2023-12-28 Samuel Holland New
[v2,09/14] x86: Implement ARCH_HAS_KERNEL_FPU_SUPPORT Unified cross-architecture kernel-mode FPU API - 1 - --- 2023-12-28 Samuel Holland New
[v2,08/14] powerpc: Implement ARCH_HAS_KERNEL_FPU_SUPPORT Unified cross-architecture kernel-mode FPU API 1 1 - --- 2023-12-28 Samuel Holland New
[v2,07/14] LoongArch: Implement ARCH_HAS_KERNEL_FPU_SUPPORT Unified cross-architecture kernel-mode FPU API 1 1 - --- 2023-12-28 Samuel Holland New
[v2,06/14] lib/raid6: Use CC_FLAGS_FPU for NEON CFLAGS Unified cross-architecture kernel-mode FPU API - 1 - --- 2023-12-28 Samuel Holland New
[v2,05/14] arm64: crypto: Use CC_FLAGS_FPU for NEON CFLAGS Unified cross-architecture kernel-mode FPU API - - - --- 2023-12-28 Samuel Holland New
[v2,04/14] arm64: Implement ARCH_HAS_KERNEL_FPU_SUPPORT Unified cross-architecture kernel-mode FPU API - 1 - --- 2023-12-28 Samuel Holland New
[v2,03/14] ARM: crypto: Use CC_FLAGS_FPU for NEON CFLAGS Unified cross-architecture kernel-mode FPU API - 1 - --- 2023-12-28 Samuel Holland New
[v2,02/14] ARM: Implement ARCH_HAS_KERNEL_FPU_SUPPORT Unified cross-architecture kernel-mode FPU API - 1 - --- 2023-12-28 Samuel Holland New
[v2,01/14] arch: Add ARCH_HAS_KERNEL_FPU_SUPPORT Unified cross-architecture kernel-mode FPU API - 1 - --- 2023-12-28 Samuel Holland New
dt-bindings: riscv: cpus: Clarify mmu-type interpretation dt-bindings: riscv: cpus: Clarify mmu-type interpretation - 1 - --- 2023-12-27 Samuel Holland New
[RFC,12/12] selftests/fpu: Allow building on other architectures Unified cross-architecture kernel-mode FPU API - 1 - --- 2023-12-08 Samuel Holland New
[RFC,11/12] selftests/fpu: Move FP code to a separate translation unit Unified cross-architecture kernel-mode FPU API - - - --- 2023-12-08 Samuel Holland New
[RFC,10/12] drm/amd/display: Use ARCH_HAS_KERNEL_FPU_SUPPORT Unified cross-architecture kernel-mode FPU API - - - --- 2023-12-08 Samuel Holland New
[RFC,09/12] riscv: Add support for kernel-mode FPU Unified cross-architecture kernel-mode FPU API - - - --- 2023-12-08 Samuel Holland New
[RFC,08/12] x86: Implement ARCH_HAS_KERNEL_FPU_SUPPORT Unified cross-architecture kernel-mode FPU API - 1 - --- 2023-12-08 Samuel Holland New
[RFC,07/12] powerpc: Implement ARCH_HAS_KERNEL_FPU_SUPPORT Unified cross-architecture kernel-mode FPU API - 1 - --- 2023-12-08 Samuel Holland New
[RFC,06/12] LoongArch: Implement ARCH_HAS_KERNEL_FPU_SUPPORT Unified cross-architecture kernel-mode FPU API 1 1 - --- 2023-12-08 Samuel Holland New
[RFC,05/12] lib/raid6: Use CC_FLAGS_FPU for NEON CFLAGS Unified cross-architecture kernel-mode FPU API - 1 - --- 2023-12-08 Samuel Holland New
[RFC,04/12] arm64: Implement ARCH_HAS_KERNEL_FPU_SUPPORT Unified cross-architecture kernel-mode FPU API - 1 - --- 2023-12-08 Samuel Holland New
[RFC,03/12] ARM: crypto: Use CC_FLAGS_FPU for NEON CFLAGS Unified cross-architecture kernel-mode FPU API - 1 - --- 2023-12-08 Samuel Holland New
[RFC,02/12] ARM: Implement ARCH_HAS_KERNEL_FPU_SUPPORT Unified cross-architecture kernel-mode FPU API - 1 - --- 2023-12-08 Samuel Holland New
[RFC,01/12] arch: Add ARCH_HAS_KERNEL_FPU_SUPPORT Unified cross-architecture kernel-mode FPU API - 1 - --- 2023-12-08 Samuel Holland New
[3/3] drm/amd/display: Support DRM_AMD_DC_FP on RISC-V riscv: Add kernel-mode FPU support for amdgpu - - - --- 2023-11-22 Samuel Holland New
[2/3] riscv: Factor out riscv-march-y to a separate Makefile riscv: Add kernel-mode FPU support for amdgpu - - - --- 2023-11-22 Samuel Holland New
[1/3] riscv: Add support for kernel-mode FPU riscv: Add kernel-mode FPU support for amdgpu - - - --- 2023-11-22 Samuel Holland New
[v3,8/8] riscv: mm: Always use ASID to flush MM contexts riscv: ASID-related and UP-related TLB flush enhancements - - - --- 2023-11-22 Samuel Holland New
[v3,7/8] riscv: mm: Preserve global TLB entries when switching contexts riscv: ASID-related and UP-related TLB flush enhancements - - - --- 2023-11-22 Samuel Holland New
[v3,6/8] riscv: mm: Make asid_bits a local variable riscv: ASID-related and UP-related TLB flush enhancements - - - --- 2023-11-22 Samuel Holland New
[v3,5/8] riscv: mm: Use a fixed layout for the MM context ID riscv: ASID-related and UP-related TLB flush enhancements - - - --- 2023-11-22 Samuel Holland New
[v3,4/8] riscv: mm: Introduce cntx2asid/cntx2version helper macros riscv: ASID-related and UP-related TLB flush enhancements - - - --- 2023-11-22 Samuel Holland New
[v3,3/8] riscv: Avoid TLB flush loops when affected by SiFive CIP-1200 riscv: ASID-related and UP-related TLB flush enhancements - - - --- 2023-11-22 Samuel Holland New
[v3,2/8] riscv: Apply SiFive CIP-1200 workaround to single-ASID sfence.vma riscv: ASID-related and UP-related TLB flush enhancements - - - --- 2023-11-22 Samuel Holland New
[v3,1/8] riscv: mm: Combine the SMP and UP TLB flush code riscv: ASID-related and UP-related TLB flush enhancements - - - --- 2023-11-22 Samuel Holland New
[net] net: axienet: Fix check for partial TX checksum [net] net: axienet: Fix check for partial TX checksum - 2 - --- 2023-11-22 Samuel Holland New
[3/3] riscv: Use the same CPU operations for all CPUs riscv: CPU operations cleanup - 1 - --- 2023-11-21 Samuel Holland New
[2/3] riscv: Remove unused members from struct cpu_operations riscv: CPU operations cleanup - 1 - --- 2023-11-21 Samuel Holland New
[1/3] riscv: Deduplicate code in setup_smp() riscv: CPU operations cleanup - 1 - --- 2023-11-21 Samuel Holland New
riscv: Remove obsolete rv32_defconfig file riscv: Remove obsolete rv32_defconfig file - 1 - --- 2023-11-21 Samuel Holland New
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