Show patches with: Series = riscv: ASID-related and UP-related TLB flush enhancements       |   8 patches
Patch Series A/R/T S/W/F Date Submitter Delegate State
[v3,8/8] riscv: mm: Always use ASID to flush MM contexts riscv: ASID-related and UP-related TLB flush enhancements - - - --- 2023-11-22 Samuel Holland New
[v3,7/8] riscv: mm: Preserve global TLB entries when switching contexts riscv: ASID-related and UP-related TLB flush enhancements - - - --- 2023-11-22 Samuel Holland New
[v3,6/8] riscv: mm: Make asid_bits a local variable riscv: ASID-related and UP-related TLB flush enhancements - - - --- 2023-11-22 Samuel Holland New
[v3,5/8] riscv: mm: Use a fixed layout for the MM context ID riscv: ASID-related and UP-related TLB flush enhancements - - - --- 2023-11-22 Samuel Holland New
[v3,4/8] riscv: mm: Introduce cntx2asid/cntx2version helper macros riscv: ASID-related and UP-related TLB flush enhancements - - - --- 2023-11-22 Samuel Holland New
[v3,3/8] riscv: Avoid TLB flush loops when affected by SiFive CIP-1200 riscv: ASID-related and UP-related TLB flush enhancements - - - --- 2023-11-22 Samuel Holland New
[v3,2/8] riscv: Apply SiFive CIP-1200 workaround to single-ASID sfence.vma riscv: ASID-related and UP-related TLB flush enhancements - - - --- 2023-11-22 Samuel Holland New
[v3,1/8] riscv: mm: Combine the SMP and UP TLB flush code riscv: ASID-related and UP-related TLB flush enhancements - - - --- 2023-11-22 Samuel Holland New