Show patches with: Series = riscv: ASID-related and UP-related TLB flush enhancements       |    State = Action Required       |   11 patches
Patch Series A/R/T S/W/F Date Submitter Delegate State
[v2,11/11] riscv: mm: Always use ASID to flush MM contexts riscv: ASID-related and UP-related TLB flush enhancements - - - --- 2023-10-28 Samuel Holland New
[v2,10/11] riscv: mm: Preserve global TLB entries when switching contexts riscv: ASID-related and UP-related TLB flush enhancements - - - --- 2023-10-28 Samuel Holland New
[v2,09/11] riscv: mm: Make asid_bits a local variable riscv: ASID-related and UP-related TLB flush enhancements - - - --- 2023-10-28 Samuel Holland New
[v2,08/11] riscv: mm: Use a fixed layout for the MM context ID riscv: ASID-related and UP-related TLB flush enhancements - - - --- 2023-10-28 Samuel Holland New
[v2,07/11] riscv: mm: Introduce cntx2asid/cntx2version helper macros riscv: ASID-related and UP-related TLB flush enhancements - - - --- 2023-10-28 Samuel Holland New
[v2,06/11] riscv: Apply SiFive CIP-1200 workaround to single-ASID sfence.vma riscv: ASID-related and UP-related TLB flush enhancements - - - --- 2023-10-28 Samuel Holland New
[v2,05/11] riscv: mm: Combine the SMP and UP TLB flush code riscv: ASID-related and UP-related TLB flush enhancements - - - --- 2023-10-28 Samuel Holland New
[v2,04/11] riscv: Improve flush_tlb_kernel_range() riscv: ASID-related and UP-related TLB flush enhancements - 1 1 --- 2023-10-28 Samuel Holland New
[v2,03/11] riscv: Make __flush_tlb_range() loop over pte instead of flushing the whole tlb riscv: ASID-related and UP-related TLB flush enhancements - 1 1 --- 2023-10-28 Samuel Holland New
[v2,02/11] riscv: Improve flush_tlb_range() for hugetlb pages riscv: ASID-related and UP-related TLB flush enhancements - - - --- 2023-10-28 Samuel Holland New
[v2,01/11] riscv: Improve tlb_flush() riscv: ASID-related and UP-related TLB flush enhancements - 1 1 --- 2023-10-28 Samuel Holland New