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[0/5] riscv: sophgo: add clock support for sg2042

Message ID cover.1699879741.git.unicorn_wang@outlook.com
Headers
Series riscv: sophgo: add clock support for sg2042 |

Message

Chen Wang Nov. 13, 2023, 1:16 p.m. UTC 
  From: Chen Wang <unicorn_wang@outlook.com>

This series adds clock controller support for sophgo sg2042.

Chen Wang (5):
  dt-bindings: clock: sophgo: Add SG2042 clock definitions
  dt-bindings: soc: sophgo: Add Sophgo syscon module
  dt-bindings: clock: sophgo: Add SG2042 bindings
  clk: sophgo: Add SG2042 clock generator driver
  riscv: dts: add clock generator for Sophgo SG2042 SoC

 .../clock/sophgo/sophgo,sg2042-clkgen.yaml    |   48 +
 .../soc/sophgo/sophgo,sg2042-syscon.yaml      |   38 +
 MAINTAINERS                                   |    8 +
 arch/riscv/boot/dts/sophgo/sg2042-clock.dtsi  |   76 +
 arch/riscv/boot/dts/sophgo/sg2042.dtsi        |   10 +
 drivers/clk/Kconfig                           |    1 +
 drivers/clk/Makefile                          |    1 +
 drivers/clk/sophgo/Kconfig                    |    8 +
 drivers/clk/sophgo/Makefile                   |    2 +
 drivers/clk/sophgo/clk-sophgo-sg2042.c        | 1259 +++++++++++++++++
 drivers/clk/sophgo/clk-sophgo-sg2042.h        |  226 +++
 include/dt-bindings/clock/sophgo-sg2042-clk.h |  169 +++
 12 files changed, 1846 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/clock/sophgo/sophgo,sg2042-clkgen.yaml
 create mode 100644 Documentation/devicetree/bindings/soc/sophgo/sophgo,sg2042-syscon.yaml
 create mode 100644 arch/riscv/boot/dts/sophgo/sg2042-clock.dtsi
 create mode 100644 drivers/clk/sophgo/Kconfig
 create mode 100644 drivers/clk/sophgo/Makefile
 create mode 100644 drivers/clk/sophgo/clk-sophgo-sg2042.c
 create mode 100644 drivers/clk/sophgo/clk-sophgo-sg2042.h
 create mode 100644 include/dt-bindings/clock/sophgo-sg2042-clk.h


base-commit: b85ea95d086471afb4ad062012a4d73cd328fa86

Comments

Conor Dooley Nov. 14, 2023, 5:31 p.m. UTC | #1 
On Mon, Nov 13, 2023 at 09:20:11PM +0800, Chen Wang wrote:
> From: Chen Wang <unicorn_wang@outlook.com>
> 
> Add clock generator node to device tree for SG2042, and enable clock for
> uart0.
> 
> Signed-off-by: Chen Wang <unicorn_wang@outlook.com>
> ---
>  arch/riscv/boot/dts/sophgo/sg2042-clock.dtsi | 76 ++++++++++++++++++++

There's no need to create an entirely new file for this.

>  arch/riscv/boot/dts/sophgo/sg2042.dtsi       | 10 +++
>  2 files changed, 86 insertions(+)
>  create mode 100644 arch/riscv/boot/dts/sophgo/sg2042-clock.dtsi
> 
> diff --git a/arch/riscv/boot/dts/sophgo/sg2042-clock.dtsi b/arch/riscv/boot/dts/sophgo/sg2042-clock.dtsi
> new file mode 100644
> index 000000000000..66d2723fab35
> --- /dev/null
> +++ b/arch/riscv/boot/dts/sophgo/sg2042-clock.dtsi
> @@ -0,0 +1,76 @@
> +// SPDX-License-Identifier: (GPL-2.0 OR MIT)
> +/*
> + * Copyright (C) 2023 Sophgo Technology Inc. All rights reserved.
> + */
> +
> +/ {
> +	cgi: oscillator {
> +		compatible = "fixed-clock";
> +		clock-frequency = <25000000>;
> +		clock-output-names = "cgi";
> +		#clock-cells = <0>;
> +	};

What actually is this oscillator?
Is it provided by another clock controller on the SoC, or is it provided
by an oscillator on the board?

> +
> +	clkgen: clock-controller {
> +		compatible = "sophgo,sg2042-clkgen";
> +		#clock-cells = <1>;
> +		system-ctrl = <&sys_ctrl>;

Why is this node not a child of the system controller?

Cheers,
Conor.
Samuel Holland Nov. 15, 2023, 2:15 a.m. UTC | #2 
On 2023-11-14 7:34 PM, Chen Wang wrote:
> On 2023/11/15 1:31, Conor Dooley wrote:
>> On Mon, Nov 13, 2023 at 09:20:11PM +0800, Chen Wang wrote:
>>> From: Chen Wang <unicorn_wang@outlook.com>
>>>
>>> Add clock generator node to device tree for SG2042, and enable clock for
>>> uart0.
>>>
>>> Signed-off-by: Chen Wang <unicorn_wang@outlook.com>
>>> ---
>>>   arch/riscv/boot/dts/sophgo/sg2042-clock.dtsi | 76 ++++++++++++++++++++
>> There's no need to create an entirely new file for this.
> Agree, I will merge this into sg2042.dtsi in next revision.
>>
>>>   arch/riscv/boot/dts/sophgo/sg2042.dtsi       | 10 +++
>>>   2 files changed, 86 insertions(+)
>>>   create mode 100644 arch/riscv/boot/dts/sophgo/sg2042-clock.dtsi
>>>
>>> diff --git a/arch/riscv/boot/dts/sophgo/sg2042-clock.dtsi
>>> b/arch/riscv/boot/dts/sophgo/sg2042-clock.dtsi
>>> new file mode 100644
>>> index 000000000000..66d2723fab35
>>> --- /dev/null
>>> +++ b/arch/riscv/boot/dts/sophgo/sg2042-clock.dtsi
>>> @@ -0,0 +1,76 @@
>>> +// SPDX-License-Identifier: (GPL-2.0 OR MIT)
>>> +/*
>>> + * Copyright (C) 2023 Sophgo Technology Inc. All rights reserved.
>>> + */
>>> +
>>> +/ {
>>> +    cgi: oscillator {
>>> +        compatible = "fixed-clock";
>>> +        clock-frequency = <25000000>;
>>> +        clock-output-names = "cgi";
>>> +        #clock-cells = <0>;
>>> +    };
>> What actually is this oscillator?
>> Is it provided by another clock controller on the SoC, or is it provided
>> by an oscillator on the board?
> 
> This oscillator is an individual ic chip outside the SoC on the board, that's
> why I list it outside soc node.
> 
> Actually the "cgi" is abbrevation for "Clock Generation IC chip".

Since the oscillator is outside the SoC, this node (or at least its
clock-frequency property) belongs in the board devicetree, not the SoC .dtsi.
See [1].

Regards,
Samuel

[1]:
https://lore.kernel.org/linux-riscv/b5401052-e803-9788-64d6-82b2737533ce@linaro.org/