[v2,00/11] Add Milk-V Pioneer RISC-V board support

  Milk-V Pioneer [1] is a developer motherboard based on SOPHON SG2042 [2]
in a standard mATX form factor. Add minimal device
tree files for the SG2042 SOC and the Milk-V Pioneer board.

Now only support basic uart drivers to boot up into a basic console.

Thanks,
Chen

---

Changes in v2:
  The patch series is based on v6.6-rc1. You can simply review or test 
  the patches at the link [4].
  - Improve format for comment of commitments as per input from last review.
  - Improve format of DTS as per input from last review.
  - Remove numa related stuff from DTS. This part is just for optimization, may
    add it later if really needed. 

Previous versions:
v1: due to it is not sent in thread, I have listed permlinks of the patchset
    [v1-0/12] ~ [v1-12/12] here for quick reference. You can simply review or
    test the patches at the link [3].

[1]: https://milkv.io/pioneer
[2]: https://en.sophgo.com/product/introduce/sg2042.html
[3]: https://github.com/unicornx/linux-riscv/commits/milkv-pioneer-minimal
[4]: https://github.com/unicornx/linux-riscv/commits/milkv-pioneer-minimal-v2
[v1-0/12]:https://lore.kernel.org/linux-riscv/20230915070856.117514-1-wangchen20@iscas.ac.cn/
[v1-1/12]:https://lore.kernel.org/linux-riscv/20230915071005.117575-1-wangchen20@iscas.ac.cn/
[v1-2/12]:https://lore.kernel.org/linux-riscv/20230915071409.117692-1-wangchen20@iscas.ac.cn/
[v1-3/12]:https://lore.kernel.org/linux-riscv/20230915072242.117935-1-wangchen20@iscas.ac.cn/
[v1-4/12]:https://lore.kernel.org/linux-riscv/20230915072333.117991-1-wangchen20@iscas.ac.cn/
[v1-5/12]:https://lore.kernel.org/linux-riscv/20230915072358.118045-1-wangchen20@iscas.ac.cn/
[v1-6/12]:https://lore.kernel.org/linux-riscv/20230915072415.118100-1-wangchen20@iscas.ac.cn/
[v1-7/12]:https://lore.kernel.org/linux-riscv/20230915072431.118154-1-wangchen20@iscas.ac.cn/
[v1-8/12]:https://lore.kernel.org/linux-riscv/20230915072451.118209-1-wangchen20@iscas.ac.cn/
[v1-9/12]:https://lore.kernel.org/linux-riscv/20230915072517.118266-1-wangchen20@iscas.ac.cn/
[v1-10/12]:https://lore.kernel.org/linux-riscv/20230915072558.118325-1-wangchen20@iscas.ac.cn/
[v1-11/12]:https://lore.kernel.org/linux-riscv/20230915072624.118388-1-wangchen20@iscas.ac.cn/
[v1-12/12]:https://lore.kernel.org/linux-riscv/20230915072653.118448-1-wangchen20@iscas.ac.cn/

---

Chen Wang (8):
  riscv: Add SOPHGO SOC family Kconfig support
  dt-bindings: vendor-prefixes: add milkv/sophgo
  dt-bindings: riscv: add sophgo sg2042 bindings
  dt-bindings: riscv: Add T-HEAD C920 compatibles
  dt-bindings: interrupt-controller: Add SOPHGO's SG2042 PLIC
  riscv: dts: add initial SOPHGO SG2042 SoC device tree
  riscv: dts: sophgo: add Milk-V Pioneer board device tree
  riscv: defconfig: enable SOPHGO SoC

Emil Renner Berthing (2):
  dt-bindings: serial: snps-dw-apb-uart: Add Sophgo SG2042 uarts
  serial: 8250_dw: Add Sophgo SG2042 support

Inochi Amaoto (1):
  dt-bindings: timer: Add Sophgo sg2042 clint

 .../sifive,plic-1.0.0.yaml                    |    1 +
 .../devicetree/bindings/riscv/cpus.yaml       |    1 +
 .../devicetree/bindings/riscv/sophgo.yaml     |   28 +
 .../bindings/serial/snps-dw-apb-uart.yaml     |    1 +
 .../bindings/timer/sifive,clint.yaml          |    8 +
 .../devicetree/bindings/vendor-prefixes.yaml  |    4 +
 MAINTAINERS                                   |    7 +
 arch/riscv/Kconfig.socs                       |    5 +
 arch/riscv/boot/dts/Makefile                  |    1 +
 arch/riscv/boot/dts/sophgo/Makefile           |    3 +
 arch/riscv/boot/dts/sophgo/sg2042-cpus.dtsi   | 1744 +++++++++++++++++
 .../boot/dts/sophgo/sg2042-milkv-pioneer.dts  |   19 +
 arch/riscv/boot/dts/sophgo/sg2042.dtsi        |  439 +++++
 arch/riscv/configs/defconfig                  |    1 +
 drivers/tty/serial/8250/8250_dw.c             |    5 +-
 15 files changed, 2265 insertions(+), 2 deletions(-)
 create mode 100644 Documentation/devicetree/bindings/riscv/sophgo.yaml
 create mode 100644 arch/riscv/boot/dts/sophgo/Makefile
 create mode 100644 arch/riscv/boot/dts/sophgo/sg2042-cpus.dtsi
 create mode 100644 arch/riscv/boot/dts/sophgo/sg2042-milkv-pioneer.dts
 create mode 100644 arch/riscv/boot/dts/sophgo/sg2042.dtsi


base-commit: 0bb80ecc33a8fb5a682236443c1e740d5c917d1d
  

On Wed, Sep 20, 2023 at 2:37 PM Chen Wang <unicornxw@gmail.com> wrote:
>
> Add new vendor strings to dt bindings.
> These new vendor strings are used by
> - Sophgo SG2042 SoC [1]
> - Milk-V Pioneer board [2], which uses SG2042 chip.
>
> [1]: https://en.sophgo.com/product/introduce/sg2042.html
> [2]: https://milkv.io/pioneer
>
> Acked-by: Xiaoguang Xing <xiaoguang.xing@sophgo.com>
> Signed-off-by: Chen Wang <wangchen20@iscas.ac.cn>
> ---
>  Documentation/devicetree/bindings/vendor-prefixes.yaml | 4 ++++
>  1 file changed, 4 insertions(+)
>
> diff --git a/Documentation/devicetree/bindings/vendor-prefixes.yaml b/Documentation/devicetree/bindings/vendor-prefixes.yaml
> index 573578db9509..fcca9e070a9a 100644
> --- a/Documentation/devicetree/bindings/vendor-prefixes.yaml
> +++ b/Documentation/devicetree/bindings/vendor-prefixes.yaml
> @@ -863,6 +863,8 @@ patternProperties:
>      description: MikroElektronika d.o.o.
>    "^mikrotik,.*":
>      description: MikroTik
> +  "^milkv,.*":
> +    description: MilkV Technology Co., Ltd
>    "^miniand,.*":
>      description: Miniand Tech
>    "^minix,.*":
> @@ -1273,6 +1275,8 @@ patternProperties:
>      description: Solomon Systech Limited
>    "^sony,.*":
>      description: Sony Corporation
> +  "^sophgo,.*":
> +    description: Sophgo Technology Inc.
>    "^sourceparts,.*":
>      description: Source Parts Inc.
>    "^spansion,.*":
> --
> 2.25.1
>
Reviewed-by: Guo Ren <guoren@kernel.org>
  

On Wed, Sep 20, 2023 at 2:38 PM Chen Wang <unicornxw@gmail.com> wrote:
>
> Add DT binding documentation for the Sophgo SG2042 Soc [1] and the
> Milk-V Pioneer board [2].
>
> [1]: https://en.sophgo.com/product/introduce/sg2042.html
> [2]: https://milkv.io/pioneer
>
> Acked-by: Chao Wei <chao.wei@sophgo.com>
> Acked-by: Xiaoguang Xing <xiaoguang.xing@sophgo.com>
> Signed-off-by: Chen Wang <wangchen20@iscas.ac.cn>
> ---
>  .../devicetree/bindings/riscv/sophgo.yaml     | 28 +++++++++++++++++++
>  MAINTAINERS                                   |  7 +++++
>  2 files changed, 35 insertions(+)
>  create mode 100644 Documentation/devicetree/bindings/riscv/sophgo.yaml
>
> diff --git a/Documentation/devicetree/bindings/riscv/sophgo.yaml b/Documentation/devicetree/bindings/riscv/sophgo.yaml
> new file mode 100644
> index 000000000000..82468ae915db
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/riscv/sophgo.yaml
> @@ -0,0 +1,28 @@
> +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
> +%YAML 1.2
> +---
> +$id: http://devicetree.org/schemas/riscv/sophgo.yaml#
> +$schema: http://devicetree.org/meta-schemas/core.yaml#
> +
> +title: Sophgo SoC-based boards
> +
> +maintainers:
> +  - Chao Wei <chao.wei@sophgo.com>
> +  - Xiaoguang Xing <xiaoguang.xing@sophgo.com>
> +
> +description:
> +  Sophgo SoC-based boards
> +
> +properties:
> +  $nodename:
> +    const: '/'
> +  compatible:
> +    oneOf:
> +      - items:
> +          - enum:
> +              - milkv,pioneer
> +          - const: sophgo,sg2042
> +
> +additionalProperties: true
> +
> +...
> diff --git a/MAINTAINERS b/MAINTAINERS
> index 90f13281d297..b74d505003e2 100644
> --- a/MAINTAINERS
> +++ b/MAINTAINERS
> @@ -20063,6 +20063,13 @@ F:     drivers/char/sonypi.c
>  F:     drivers/platform/x86/sony-laptop.c
>  F:     include/linux/sony-laptop.h
>
> +SOPHGO DEVICETREES
> +M:     Xiaoguang Xing <xiaoguang.xing@sophgo.com>
> +M:     Chao Wei <chao.wei@sophgo.com>
> +S:     Maintained
> +F:     Documentation/devicetree/bindings/riscv/sophgo.yaml
> +F:     arch/riscv/boot/dts/sophgo/
> +
>  SOUND
>  M:     Jaroslav Kysela <perex@perex.cz>
>  M:     Takashi Iwai <tiwai@suse.com>
> --
> 2.25.1
>
LGTM

Reviewed-by: Guo Ren <guoren@kernel.org>
  

On Wed, Sep 20, 2023 at 2:38 PM Chen Wang <unicornxw@gmail.com> wrote:
>
> The C920 is RISC-V CPU cores from T-HEAD Semiconductor.
> Notably, the C920 core is used in the SOPHGO SG2042 SoC.
>
> Acked-by: Xiaoguang Xing <xiaoguang.xing@sophgo.com>
> Signed-off-by: Chen Wang <wangchen20@iscas.ac.cn>
> ---
>  Documentation/devicetree/bindings/riscv/cpus.yaml | 1 +
>  1 file changed, 1 insertion(+)
>
> diff --git a/Documentation/devicetree/bindings/riscv/cpus.yaml b/Documentation/devicetree/bindings/riscv/cpus.yaml
> index 38c0b5213736..185a0191bad6 100644
> --- a/Documentation/devicetree/bindings/riscv/cpus.yaml
> +++ b/Documentation/devicetree/bindings/riscv/cpus.yaml
> @@ -47,6 +47,7 @@ properties:
>                - sifive,u74-mc
>                - thead,c906
>                - thead,c910
> +              - thead,c920
Reviewed-by: Guo Ren <guoren@kernel.org>

>            - const: riscv
>        - items:
>            - enum:
> --
> 2.25.1
>
  

On Wed, Sep 20, 2023 at 2:39 PM Chen Wang <unicornxw@gmail.com> wrote:
>
> Add compatible string for SOPHGO SG2042 plic.
>
> Acked-by: Xiaoguang Xing <xiaoguang.xing@sophgo.com>
> Signed-off-by: Chen Wang <wangchen20@iscas.ac.cn>
> ---
>  .../bindings/interrupt-controller/sifive,plic-1.0.0.yaml         | 1 +
>  1 file changed, 1 insertion(+)
>
> diff --git a/Documentation/devicetree/bindings/interrupt-controller/sifive,plic-1.0.0.yaml b/Documentation/devicetree/bindings/interrupt-controller/sifive,plic-1.0.0.yaml
> index dc1f28e55266..16f9c4760c0f 100644
> --- a/Documentation/devicetree/bindings/interrupt-controller/sifive,plic-1.0.0.yaml
> +++ b/Documentation/devicetree/bindings/interrupt-controller/sifive,plic-1.0.0.yaml
> @@ -65,6 +65,7 @@ properties:
>        - items:
>            - enum:
>                - allwinner,sun20i-d1-plic
> +              - sophgo,sg2042-plic
>                - thead,th1520-plic
>            - const: thead,c900-plic
>        - items:
> --
> 2.25.1
>
Reviewed-by: Guo Ren <guoren@kernel.org>
  

On Wed, Sep 20, 2023 at 2:40 PM Chen Wang <unicornxw@gmail.com> wrote:
>
> From: Emil Renner Berthing <emil.renner.berthing@canonical.com>
>
> Add compatible for the uarts on the Sophgo SG2042 RISC-V SoC.
>
> Signed-off-by: Emil Renner Berthing <emil.renner.berthing@canonical.com>
> Signed-off-by: Chen Wang <wangchen20@iscas.ac.cn>
> ---
>  Documentation/devicetree/bindings/serial/snps-dw-apb-uart.yaml | 1 +
>  1 file changed, 1 insertion(+)
>
> diff --git a/Documentation/devicetree/bindings/serial/snps-dw-apb-uart.yaml b/Documentation/devicetree/bindings/serial/snps-dw-apb-uart.yaml
> index 17c553123f96..011d89e6df0f 100644
> --- a/Documentation/devicetree/bindings/serial/snps-dw-apb-uart.yaml
> +++ b/Documentation/devicetree/bindings/serial/snps-dw-apb-uart.yaml
> @@ -45,6 +45,7 @@ properties:
>            - const: snps,dw-apb-uart
>        - items:
>            - enum:
> +              - sophgo,sg2042-uart
>                - starfive,jh7100-hsuart
>                - starfive,jh7100-uart
>            - const: snps,dw-apb-uart
> --
> 2.25.1
>
LGTM

Reviewed-by: Guo Ren <guoren@kernel.og>
  

On Wed, Sep 20, 2023 at 2:41 PM Chen Wang <unicornxw@gmail.com> wrote:
>
> Enable SOPHGO SoC config in defconfig to allow the default
> upstream kernel to boot on Milk-V Pioneer board.
>
> Signed-off-by: Chen Wang <wangchen20@iscas.ac.cn>
> ---
>  arch/riscv/configs/defconfig | 1 +
>  1 file changed, 1 insertion(+)
>
> diff --git a/arch/riscv/configs/defconfig b/arch/riscv/configs/defconfig
> index ab86ec3b9eab..bf737cfa1d2c 100644
> --- a/arch/riscv/configs/defconfig
> +++ b/arch/riscv/configs/defconfig
> @@ -32,6 +32,7 @@ CONFIG_SOC_SIFIVE=y
>  CONFIG_SOC_STARFIVE=y
>  CONFIG_ARCH_SUNXI=y
>  CONFIG_SOC_VIRT=y
> +CONFIG_ARCH_SOPHGO=y
>  CONFIG_SMP=y
>  CONFIG_HOTPLUG_CPU=y
>  CONFIG_PM=y
> --
> 2.25.1
>
LGTM

Reviewed-by: Guo Ren <guoren@kernel.org>
  

On Wed, Sep 20, 2023 at 2:39 PM Chen Wang <unicornxw@gmail.com> wrote:
>
> From: Inochi Amaoto <inochiama@outlook.com>
>
> Add two new compatible string formatted like `C9xx-clint-xxx` to identify
> the timer and ipi device separately, and do not allow c900-clint as the
> fallback to avoid conflict.
Please explain more about the c900-clint mtimer & mswi, why do we need
to separate the c900-clint into two pieces? When could we use
c900-clint which eases dts design?

>
> Signed-off-by: Inochi Amaoto <inochiama@outlook.com>
> Signed-off-by: Chen Wang <wangchen20@iscas.ac.cn>
> ---
>  Documentation/devicetree/bindings/timer/sifive,clint.yaml | 8 ++++++++
>  1 file changed, 8 insertions(+)
>
> diff --git a/Documentation/devicetree/bindings/timer/sifive,clint.yaml b/Documentation/devicetree/bindings/timer/sifive,clint.yaml
> index a0185e15a42f..ae69696c5c75 100644
> --- a/Documentation/devicetree/bindings/timer/sifive,clint.yaml
> +++ b/Documentation/devicetree/bindings/timer/sifive,clint.yaml
> @@ -39,6 +39,14 @@ properties:
>                - allwinner,sun20i-d1-clint
>                - thead,th1520-clint
>            - const: thead,c900-clint
> +      - items:
> +          - enum:
> +              - sophgo,sg2042-clint-mtimer
> +          - const: thead,c900-clint-mtimer
> +      - items:
> +          - enum:
> +              - sophgo,sg2042-clint-mswi
> +          - const: thead,c900-clint-mswi
>        - items:
>            - const: sifive,clint0
>            - const: riscv,clint0
> --
> 2.25.1
>
  

On Wed, Sep 20, 2023 at 02:41:12PM +0800, Chen Wang wrote:
> Enable SOPHGO SoC config in defconfig to allow the default
> upstream kernel to boot on Milk-V Pioneer board.
> 
> Signed-off-by: Chen Wang <wangchen20@iscas.ac.cn>

Acked-by: Conor Dooley <conor.dooley@microchip.com>

> ---
>  arch/riscv/configs/defconfig | 1 +
>  1 file changed, 1 insertion(+)
> 
> diff --git a/arch/riscv/configs/defconfig b/arch/riscv/configs/defconfig
> index ab86ec3b9eab..bf737cfa1d2c 100644
> --- a/arch/riscv/configs/defconfig
> +++ b/arch/riscv/configs/defconfig
> @@ -32,6 +32,7 @@ CONFIG_SOC_SIFIVE=y
>  CONFIG_SOC_STARFIVE=y
>  CONFIG_ARCH_SUNXI=y
>  CONFIG_SOC_VIRT=y
> +CONFIG_ARCH_SOPHGO=y
>  CONFIG_SMP=y
>  CONFIG_HOTPLUG_CPU=y
>  CONFIG_PM=y
> -- 
> 2.25.1
>
  

Regards,

unicornx

Conor Dooley <conor.dooley@microchip.com> 于2023年9月20日周三 16:23写道：
>
> Yo,
>
> On Wed, Sep 20, 2023 at 02:37:28PM +0800, Chen Wang wrote:
> > Add new vendor strings to dt bindings.
> > These new vendor strings are used by
> > - Sophgo SG2042 SoC [1]
> > - Milk-V Pioneer board [2], which uses SG2042 chip.
> >
> > [1]: https://en.sophgo.com/product/introduce/sg2042.html
> > [2]: https://milkv.io/pioneer
>
> If you resend, make these link tags please. Otherwise,
> Reviewed-by: Conor Dooley <conor.dooley@microchip.com>
>
Sure, I will correct them in next revision. Thanks.

> Thanks,
> Conor.
>
> > Acked-by: Xiaoguang Xing <xiaoguang.xing@sophgo.com>
> > Signed-off-by: Chen Wang <wangchen20@iscas.ac.cn>
> > ---
> >  Documentation/devicetree/bindings/vendor-prefixes.yaml | 4 ++++
> >  1 file changed, 4 insertions(+)
> >
> > diff --git a/Documentation/devicetree/bindings/vendor-prefixes.yaml b/Documentation/devicetree/bindings/vendor-prefixes.yaml
> > index 573578db9509..fcca9e070a9a 100644
> > --- a/Documentation/devicetree/bindings/vendor-prefixes.yaml
> > +++ b/Documentation/devicetree/bindings/vendor-prefixes.yaml
> > @@ -863,6 +863,8 @@ patternProperties:
> >      description: MikroElektronika d.o.o.
> >    "^mikrotik,.*":
> >      description: MikroTik
> > +  "^milkv,.*":
> > +    description: MilkV Technology Co., Ltd
> >    "^miniand,.*":
> >      description: Miniand Tech
> >    "^minix,.*":
> > @@ -1273,6 +1275,8 @@ patternProperties:
> >      description: Solomon Systech Limited
> >    "^sony,.*":
> >      description: Sony Corporation
> > +  "^sophgo,.*":
> > +    description: Sophgo Technology Inc.
> >    "^sourceparts,.*":
> >      description: Source Parts Inc.
> >    "^spansion,.*":
> > --
> > 2.25.1
> >
  

On Wed, Sep 20, 2023 at 02:33:48PM +0800, Chen Wang wrote:
> Milk-V Pioneer [1] is a developer motherboard based on SOPHON SG2042 [2]
> in a standard mATX form factor. Add minimal device
> tree files for the SG2042 SOC and the Milk-V Pioneer board.

Please run dtbs_check with W=1 set & fix the below issues:

sg2042-cpus.dtsi:1600.25-1607.5: Warning (unit_address_vs_reg): /cpus/l2-cache@0: node has a unit name, but no reg or ranges property
sg2042-cpus.dtsi:1609.25-1616.5: Warning (unit_address_vs_reg): /cpus/l2-cache@1: node has a unit name, but no reg or ranges property
sg2042-cpus.dtsi:1618.25-1625.5: Warning (unit_address_vs_reg): /cpus/l2-cache@2: node has a unit name, but no reg or ranges property
sg2042-cpus.dtsi:1627.25-1634.5: Warning (unit_address_vs_reg): /cpus/l2-cache@3: node has a unit name, but no reg or ranges property
sg2042-cpus.dtsi:1636.25-1643.5: Warning (unit_address_vs_reg): /cpus/l2-cache@4: node has a unit name, but no reg or ranges property
sg2042-cpus.dtsi:1645.25-1652.5: Warning (unit_address_vs_reg): /cpus/l2-cache@5: node has a unit name, but no reg or ranges property
sg2042-cpus.dtsi:1654.25-1661.5: Warning (unit_address_vs_reg): /cpus/l2-cache@6: node has a unit name, but no reg or ranges property
sg2042-cpus.dtsi:1663.25-1670.5: Warning (unit_address_vs_reg): /cpus/l2-cache@7: node has a unit name, but no reg or ranges property
sg2042-cpus.dtsi:1672.25-1679.5: Warning (unit_address_vs_reg): /cpus/l2-cache@8: node has a unit name, but no reg or ranges property
sg2042-cpus.dtsi:1681.25-1688.5: Warning (unit_address_vs_reg): /cpus/l2-cache@9: node has a unit name, but no reg or ranges property
sg2042-cpus.dtsi:1690.27-1697.5: Warning (unit_address_vs_reg): /cpus/l2-cache@10: node has a unit name, but no reg or ranges property
sg2042-cpus.dtsi:1699.27-1706.5: Warning (unit_address_vs_reg): /cpus/l2-cache@11: node has a unit name, but no reg or ranges property
sg2042-cpus.dtsi:1708.27-1715.5: Warning (unit_address_vs_reg): /cpus/l2-cache@12: node has a unit name, but no reg or ranges property
sg2042-cpus.dtsi:1717.27-1724.5: Warning (unit_address_vs_reg): /cpus/l2-cache@13: node has a unit name, but no reg or ranges property
sg2042-cpus.dtsi:1726.27-1733.5: Warning (unit_address_vs_reg): /cpus/l2-cache@14: node has a unit name, but no reg or ranges property
sg2042-cpus.dtsi:1735.27-1742.5: Warning (unit_address_vs_reg): /cpus/l2-cache@15: node has a unit name, but no reg or ranges property
sg2042-cpus.dtsi:256.15-275.5: Warning (unique_unit_address_if_enabled): /cpus/cpu@0: duplicate unit-address (also used in node /cpus/l2-cache@0)
sg2042-cpus.dtsi:277.15-296.5: Warning (unique_unit_address_if_enabled): /cpus/cpu@1: duplicate unit-address (also used in node /cpus/l2-cache@1)
sg2042-cpus.dtsi:298.15-317.5: Warning (unique_unit_address_if_enabled): /cpus/cpu@2: duplicate unit-address (also used in node /cpus/l2-cache@2)
sg2042-cpus.dtsi:319.15-338.5: Warning (unique_unit_address_if_enabled): /cpus/cpu@3: duplicate unit-address (also used in node /cpus/l2-cache@3)
sg2042-cpus.dtsi:340.15-359.5: Warning (unique_unit_address_if_enabled): /cpus/cpu@4: duplicate unit-address (also used in node /cpus/l2-cache@4)
sg2042-cpus.dtsi:361.15-380.5: Warning (unique_unit_address_if_enabled): /cpus/cpu@5: duplicate unit-address (also used in node /cpus/l2-cache@5)
sg2042-cpus.dtsi:382.15-401.5: Warning (unique_unit_address_if_enabled): /cpus/cpu@6: duplicate unit-address (also used in node /cpus/l2-cache@6)
sg2042-cpus.dtsi:403.15-422.5: Warning (unique_unit_address_if_enabled): /cpus/cpu@7: duplicate unit-address (also used in node /cpus/l2-cache@7)
sg2042-cpus.dtsi:424.15-443.5: Warning (unique_unit_address_if_enabled): /cpus/cpu@8: duplicate unit-address (also used in node /cpus/l2-cache@8)
sg2042-cpus.dtsi:445.15-464.5: Warning (unique_unit_address_if_enabled): /cpus/cpu@9: duplicate unit-address (also used in node /cpus/l2-cache@9)
sg2042-cpus.dtsi:466.17-485.5: Warning (unique_unit_address_if_enabled): /cpus/cpu@10: duplicate unit-address (also used in node /cpus/l2-cache@10)
sg2042-cpus.dtsi:487.17-506.5: Warning (unique_unit_address_if_enabled): /cpus/cpu@11: duplicate unit-address (also used in node /cpus/l2-cache@11)
sg2042-cpus.dtsi:508.17-527.5: Warning (unique_unit_address_if_enabled): /cpus/cpu@12: duplicate unit-address (also used in node /cpus/l2-cache@12)
sg2042-cpus.dtsi:529.17-548.5: Warning (unique_unit_address_if_enabled): /cpus/cpu@13: duplicate unit-address (also used in node /cpus/l2-cache@13)
sg2042-cpus.dtsi:550.17-569.5: Warning (unique_unit_address_if_enabled): /cpus/cpu@14: duplicate unit-address (also used in node /cpus/l2-cache@14)
sg2042-cpus.dtsi:571.17-590.5: Warning (unique_unit_address_if_enabled): /cpus/cpu@15: duplicate unit-address (also used in node /cpus/l2-cache@15)

Thanks,
Conor.
  

On Tue, 19 Sep 2023 23:33:48 PDT (-0700), unicornxw@gmail.com wrote:
> Milk-V Pioneer [1] is a developer motherboard based on SOPHON SG2042 [2]
> in a standard mATX form factor. Add minimal device
> tree files for the SG2042 SOC and the Milk-V Pioneer board.
>
> Now only support basic uart drivers to boot up into a basic console.
>
> Thanks,
> Chen
>
> ---
>
> Changes in v2:
>   The patch series is based on v6.6-rc1. You can simply review or test
>   the patches at the link [4].
>   - Improve format for comment of commitments as per input from last review.
>   - Improve format of DTS as per input from last review.
>   - Remove numa related stuff from DTS. This part is just for optimization, may
>     add it later if really needed.
>
> Previous versions:
> v1: due to it is not sent in thread, I have listed permlinks of the patchset
>     [v1-0/12] ~ [v1-12/12] here for quick reference. You can simply review or
>     test the patches at the link [3].
>
> [1]: https://milkv.io/pioneer
> [2]: https://en.sophgo.com/product/introduce/sg2042.html
> [3]: https://github.com/unicornx/linux-riscv/commits/milkv-pioneer-minimal
> [4]: https://github.com/unicornx/linux-riscv/commits/milkv-pioneer-minimal-v2
> [v1-0/12]:https://lore.kernel.org/linux-riscv/20230915070856.117514-1-wangchen20@iscas.ac.cn/
> [v1-1/12]:https://lore.kernel.org/linux-riscv/20230915071005.117575-1-wangchen20@iscas.ac.cn/
> [v1-2/12]:https://lore.kernel.org/linux-riscv/20230915071409.117692-1-wangchen20@iscas.ac.cn/
> [v1-3/12]:https://lore.kernel.org/linux-riscv/20230915072242.117935-1-wangchen20@iscas.ac.cn/
> [v1-4/12]:https://lore.kernel.org/linux-riscv/20230915072333.117991-1-wangchen20@iscas.ac.cn/
> [v1-5/12]:https://lore.kernel.org/linux-riscv/20230915072358.118045-1-wangchen20@iscas.ac.cn/
> [v1-6/12]:https://lore.kernel.org/linux-riscv/20230915072415.118100-1-wangchen20@iscas.ac.cn/
> [v1-7/12]:https://lore.kernel.org/linux-riscv/20230915072431.118154-1-wangchen20@iscas.ac.cn/
> [v1-8/12]:https://lore.kernel.org/linux-riscv/20230915072451.118209-1-wangchen20@iscas.ac.cn/
> [v1-9/12]:https://lore.kernel.org/linux-riscv/20230915072517.118266-1-wangchen20@iscas.ac.cn/
> [v1-10/12]:https://lore.kernel.org/linux-riscv/20230915072558.118325-1-wangchen20@iscas.ac.cn/
> [v1-11/12]:https://lore.kernel.org/linux-riscv/20230915072624.118388-1-wangchen20@iscas.ac.cn/
> [v1-12/12]:https://lore.kernel.org/linux-riscv/20230915072653.118448-1-wangchen20@iscas.ac.cn/
>
> ---
>
> Chen Wang (8):
>   riscv: Add SOPHGO SOC family Kconfig support
>   dt-bindings: vendor-prefixes: add milkv/sophgo
>   dt-bindings: riscv: add sophgo sg2042 bindings
>   dt-bindings: riscv: Add T-HEAD C920 compatibles
>   dt-bindings: interrupt-controller: Add SOPHGO's SG2042 PLIC
>   riscv: dts: add initial SOPHGO SG2042 SoC device tree
>   riscv: dts: sophgo: add Milk-V Pioneer board device tree
>   riscv: defconfig: enable SOPHGO SoC
>
> Emil Renner Berthing (2):
>   dt-bindings: serial: snps-dw-apb-uart: Add Sophgo SG2042 uarts
>   serial: 8250_dw: Add Sophgo SG2042 support
>
> Inochi Amaoto (1):
>   dt-bindings: timer: Add Sophgo sg2042 clint
>
>  .../sifive,plic-1.0.0.yaml                    |    1 +
>  .../devicetree/bindings/riscv/cpus.yaml       |    1 +
>  .../devicetree/bindings/riscv/sophgo.yaml     |   28 +
>  .../bindings/serial/snps-dw-apb-uart.yaml     |    1 +
>  .../bindings/timer/sifive,clint.yaml          |    8 +
>  .../devicetree/bindings/vendor-prefixes.yaml  |    4 +
>  MAINTAINERS                                   |    7 +
>  arch/riscv/Kconfig.socs                       |    5 +
>  arch/riscv/boot/dts/Makefile                  |    1 +
>  arch/riscv/boot/dts/sophgo/Makefile           |    3 +
>  arch/riscv/boot/dts/sophgo/sg2042-cpus.dtsi   | 1744 +++++++++++++++++
>  .../boot/dts/sophgo/sg2042-milkv-pioneer.dts  |   19 +
>  arch/riscv/boot/dts/sophgo/sg2042.dtsi        |  439 +++++
>  arch/riscv/configs/defconfig                  |    1 +
>  drivers/tty/serial/8250/8250_dw.c             |    5 +-
>  15 files changed, 2265 insertions(+), 2 deletions(-)
>  create mode 100644 Documentation/devicetree/bindings/riscv/sophgo.yaml
>  create mode 100644 arch/riscv/boot/dts/sophgo/Makefile
>  create mode 100644 arch/riscv/boot/dts/sophgo/sg2042-cpus.dtsi
>  create mode 100644 arch/riscv/boot/dts/sophgo/sg2042-milkv-pioneer.dts
>  create mode 100644 arch/riscv/boot/dts/sophgo/sg2042.dtsi

Given this is the first sg2042 and it appears to have a few errata (the 
FP rounding issues and the special fence for starvation), I think we 
want to make sure we figure out how to provide that information to 
userspace.

> base-commit: 0bb80ecc33a8fb5a682236443c1e740d5c917d1d
  

Regards,

unicornx

Conor Dooley <conor.dooley@microchip.com> 于2023年9月20日周三 18:01写道：
>
> On Wed, Sep 20, 2023 at 02:33:48PM +0800, Chen Wang wrote:
> > Milk-V Pioneer [1] is a developer motherboard based on SOPHON SG2042 [2]
> > in a standard mATX form factor. Add minimal device
> > tree files for the SG2042 SOC and the Milk-V Pioneer board.
>
> Please run dtbs_check with W=1 set & fix the below issues:
>
> sg2042-cpus.dtsi:1600.25-1607.5: Warning (unit_address_vs_reg): /cpus/l2-cache@0: node has a unit name, but no reg or ranges property
> sg2042-cpus.dtsi:1609.25-1616.5: Warning (unit_address_vs_reg): /cpus/l2-cache@1: node has a unit name, but no reg or ranges property
> sg2042-cpus.dtsi:1618.25-1625.5: Warning (unit_address_vs_reg): /cpus/l2-cache@2: node has a unit name, but no reg or ranges property
> sg2042-cpus.dtsi:1627.25-1634.5: Warning (unit_address_vs_reg): /cpus/l2-cache@3: node has a unit name, but no reg or ranges property
> sg2042-cpus.dtsi:1636.25-1643.5: Warning (unit_address_vs_reg): /cpus/l2-cache@4: node has a unit name, but no reg or ranges property
> sg2042-cpus.dtsi:1645.25-1652.5: Warning (unit_address_vs_reg): /cpus/l2-cache@5: node has a unit name, but no reg or ranges property
> sg2042-cpus.dtsi:1654.25-1661.5: Warning (unit_address_vs_reg): /cpus/l2-cache@6: node has a unit name, but no reg or ranges property
> sg2042-cpus.dtsi:1663.25-1670.5: Warning (unit_address_vs_reg): /cpus/l2-cache@7: node has a unit name, but no reg or ranges property
> sg2042-cpus.dtsi:1672.25-1679.5: Warning (unit_address_vs_reg): /cpus/l2-cache@8: node has a unit name, but no reg or ranges property
> sg2042-cpus.dtsi:1681.25-1688.5: Warning (unit_address_vs_reg): /cpus/l2-cache@9: node has a unit name, but no reg or ranges property
> sg2042-cpus.dtsi:1690.27-1697.5: Warning (unit_address_vs_reg): /cpus/l2-cache@10: node has a unit name, but no reg or ranges property
> sg2042-cpus.dtsi:1699.27-1706.5: Warning (unit_address_vs_reg): /cpus/l2-cache@11: node has a unit name, but no reg or ranges property
> sg2042-cpus.dtsi:1708.27-1715.5: Warning (unit_address_vs_reg): /cpus/l2-cache@12: node has a unit name, but no reg or ranges property
> sg2042-cpus.dtsi:1717.27-1724.5: Warning (unit_address_vs_reg): /cpus/l2-cache@13: node has a unit name, but no reg or ranges property
> sg2042-cpus.dtsi:1726.27-1733.5: Warning (unit_address_vs_reg): /cpus/l2-cache@14: node has a unit name, but no reg or ranges property
> sg2042-cpus.dtsi:1735.27-1742.5: Warning (unit_address_vs_reg): /cpus/l2-cache@15: node has a unit name, but no reg or ranges property
> sg2042-cpus.dtsi:256.15-275.5: Warning (unique_unit_address_if_enabled): /cpus/cpu@0: duplicate unit-address (also used in node /cpus/l2-cache@0)
> sg2042-cpus.dtsi:277.15-296.5: Warning (unique_unit_address_if_enabled): /cpus/cpu@1: duplicate unit-address (also used in node /cpus/l2-cache@1)
> sg2042-cpus.dtsi:298.15-317.5: Warning (unique_unit_address_if_enabled): /cpus/cpu@2: duplicate unit-address (also used in node /cpus/l2-cache@2)
> sg2042-cpus.dtsi:319.15-338.5: Warning (unique_unit_address_if_enabled): /cpus/cpu@3: duplicate unit-address (also used in node /cpus/l2-cache@3)
> sg2042-cpus.dtsi:340.15-359.5: Warning (unique_unit_address_if_enabled): /cpus/cpu@4: duplicate unit-address (also used in node /cpus/l2-cache@4)
> sg2042-cpus.dtsi:361.15-380.5: Warning (unique_unit_address_if_enabled): /cpus/cpu@5: duplicate unit-address (also used in node /cpus/l2-cache@5)
> sg2042-cpus.dtsi:382.15-401.5: Warning (unique_unit_address_if_enabled): /cpus/cpu@6: duplicate unit-address (also used in node /cpus/l2-cache@6)
> sg2042-cpus.dtsi:403.15-422.5: Warning (unique_unit_address_if_enabled): /cpus/cpu@7: duplicate unit-address (also used in node /cpus/l2-cache@7)
> sg2042-cpus.dtsi:424.15-443.5: Warning (unique_unit_address_if_enabled): /cpus/cpu@8: duplicate unit-address (also used in node /cpus/l2-cache@8)
> sg2042-cpus.dtsi:445.15-464.5: Warning (unique_unit_address_if_enabled): /cpus/cpu@9: duplicate unit-address (also used in node /cpus/l2-cache@9)
> sg2042-cpus.dtsi:466.17-485.5: Warning (unique_unit_address_if_enabled): /cpus/cpu@10: duplicate unit-address (also used in node /cpus/l2-cache@10)
> sg2042-cpus.dtsi:487.17-506.5: Warning (unique_unit_address_if_enabled): /cpus/cpu@11: duplicate unit-address (also used in node /cpus/l2-cache@11)
> sg2042-cpus.dtsi:508.17-527.5: Warning (unique_unit_address_if_enabled): /cpus/cpu@12: duplicate unit-address (also used in node /cpus/l2-cache@12)
> sg2042-cpus.dtsi:529.17-548.5: Warning (unique_unit_address_if_enabled): /cpus/cpu@13: duplicate unit-address (also used in node /cpus/l2-cache@13)
> sg2042-cpus.dtsi:550.17-569.5: Warning (unique_unit_address_if_enabled): /cpus/cpu@14: duplicate unit-address (also used in node /cpus/l2-cache@14)
> sg2042-cpus.dtsi:571.17-590.5: Warning (unique_unit_address_if_enabled): /cpus/cpu@15: duplicate unit-address (also used in node /cpus/l2-cache@15)
>
> Thanks,
> Conor.

I find the rootcause is due to following code in DTS:
```
                l2_cache0: l2-cache@0 {
                        compatible = "cache";
                        cache-block-size = <64>;
                        cache-level = <2>;
                        cache-size = <1048576>;
                        cache-sets = <1024>;
                        cache-unified;
                };
```
To differ 16 l2-cache controller, we add <unit-address>, but due to
the l2-cache controller on sg2042 has no address, no reg property is
added here. That's why dtbs_check warns "node has a unit name, but no
reg or ranges property". I just double-confirmed with sophgo
engineers, they  told me there is really no address for the cache
controller for sg2042.

One solution I use here is to provide unique name for the l2-cache
node. I learn this from  "arch/arm64/boot/dts/hisilicon/hi3660.dtsi"
and seems this work and pass dtbs_check with W=1. For example:
```
                l2_cache0: l2-cache0 {
                        compatible = "cache";
                        cache-block-size = <64>;
                        cache-level = <2>;
                        cache-size = <1048576>;
                        cache-sets = <1024>;
                        cache-unified;
                };

                l2_cache1: l2-cache1 {
                        compatible = "cache";
                        cache-block-size = <64>;
                        cache-level = <2>;
                        cache-size = <1048576>;
                        cache-sets = <1024>;
                        cache-unified;
                };
                ......
```
But I remember as mentioned in
https://devicetree-specification.readthedocs.io/en/latest/chapter2-devicetree-basics.html#generic-names-recommendation,
node names should be generic. So I have two questions here:
- Should I use "cache-controller" instead of "l2-cache", though I see
"l2-cache" is used in many places but not listed in
devicetree-specification.
- Even if I replace "l2-cache" with "cache-controller", I think
"cache-controller0", "cache-controller1" ... are not generic name, but
due to sg2042 does not have address for cache controller, how to
handle this problem?
  

On Fri, Sep 22, 2023 at 06:24:25PM +0800, Chen Wang wrote:
> Regards,
> 
> unicornx
> 
> Conor Dooley <conor.dooley@microchip.com> 于2023年9月20日周三 18:01写道：
> >
> > On Wed, Sep 20, 2023 at 02:33:48PM +0800, Chen Wang wrote:
> > > Milk-V Pioneer [1] is a developer motherboard based on SOPHON SG2042 [2]
> > > in a standard mATX form factor. Add minimal device
> > > tree files for the SG2042 SOC and the Milk-V Pioneer board.
> >
> > Please run dtbs_check with W=1 set & fix the below issues:
> >
> > sg2042-cpus.dtsi:1600.25-1607.5: Warning (unit_address_vs_reg): /cpus/l2-cache@0: node has a unit name, but no reg or ranges property
> > sg2042-cpus.dtsi:1609.25-1616.5: Warning (unit_address_vs_reg): /cpus/l2-cache@1: node has a unit name, but no reg or ranges property
> > sg2042-cpus.dtsi:1618.25-1625.5: Warning (unit_address_vs_reg): /cpus/l2-cache@2: node has a unit name, but no reg or ranges property
> > sg2042-cpus.dtsi:1627.25-1634.5: Warning (unit_address_vs_reg): /cpus/l2-cache@3: node has a unit name, but no reg or ranges property
> > sg2042-cpus.dtsi:1636.25-1643.5: Warning (unit_address_vs_reg): /cpus/l2-cache@4: node has a unit name, but no reg or ranges property
> > sg2042-cpus.dtsi:1645.25-1652.5: Warning (unit_address_vs_reg): /cpus/l2-cache@5: node has a unit name, but no reg or ranges property
> > sg2042-cpus.dtsi:1654.25-1661.5: Warning (unit_address_vs_reg): /cpus/l2-cache@6: node has a unit name, but no reg or ranges property
> > sg2042-cpus.dtsi:1663.25-1670.5: Warning (unit_address_vs_reg): /cpus/l2-cache@7: node has a unit name, but no reg or ranges property
> > sg2042-cpus.dtsi:1672.25-1679.5: Warning (unit_address_vs_reg): /cpus/l2-cache@8: node has a unit name, but no reg or ranges property
> > sg2042-cpus.dtsi:1681.25-1688.5: Warning (unit_address_vs_reg): /cpus/l2-cache@9: node has a unit name, but no reg or ranges property
> > sg2042-cpus.dtsi:1690.27-1697.5: Warning (unit_address_vs_reg): /cpus/l2-cache@10: node has a unit name, but no reg or ranges property
> > sg2042-cpus.dtsi:1699.27-1706.5: Warning (unit_address_vs_reg): /cpus/l2-cache@11: node has a unit name, but no reg or ranges property
> > sg2042-cpus.dtsi:1708.27-1715.5: Warning (unit_address_vs_reg): /cpus/l2-cache@12: node has a unit name, but no reg or ranges property
> > sg2042-cpus.dtsi:1717.27-1724.5: Warning (unit_address_vs_reg): /cpus/l2-cache@13: node has a unit name, but no reg or ranges property
> > sg2042-cpus.dtsi:1726.27-1733.5: Warning (unit_address_vs_reg): /cpus/l2-cache@14: node has a unit name, but no reg or ranges property
> > sg2042-cpus.dtsi:1735.27-1742.5: Warning (unit_address_vs_reg): /cpus/l2-cache@15: node has a unit name, but no reg or ranges property
> > sg2042-cpus.dtsi:256.15-275.5: Warning (unique_unit_address_if_enabled): /cpus/cpu@0: duplicate unit-address (also used in node /cpus/l2-cache@0)
> > sg2042-cpus.dtsi:277.15-296.5: Warning (unique_unit_address_if_enabled): /cpus/cpu@1: duplicate unit-address (also used in node /cpus/l2-cache@1)
> > sg2042-cpus.dtsi:298.15-317.5: Warning (unique_unit_address_if_enabled): /cpus/cpu@2: duplicate unit-address (also used in node /cpus/l2-cache@2)
> > sg2042-cpus.dtsi:319.15-338.5: Warning (unique_unit_address_if_enabled): /cpus/cpu@3: duplicate unit-address (also used in node /cpus/l2-cache@3)
> > sg2042-cpus.dtsi:340.15-359.5: Warning (unique_unit_address_if_enabled): /cpus/cpu@4: duplicate unit-address (also used in node /cpus/l2-cache@4)
> > sg2042-cpus.dtsi:361.15-380.5: Warning (unique_unit_address_if_enabled): /cpus/cpu@5: duplicate unit-address (also used in node /cpus/l2-cache@5)
> > sg2042-cpus.dtsi:382.15-401.5: Warning (unique_unit_address_if_enabled): /cpus/cpu@6: duplicate unit-address (also used in node /cpus/l2-cache@6)
> > sg2042-cpus.dtsi:403.15-422.5: Warning (unique_unit_address_if_enabled): /cpus/cpu@7: duplicate unit-address (also used in node /cpus/l2-cache@7)
> > sg2042-cpus.dtsi:424.15-443.5: Warning (unique_unit_address_if_enabled): /cpus/cpu@8: duplicate unit-address (also used in node /cpus/l2-cache@8)
> > sg2042-cpus.dtsi:445.15-464.5: Warning (unique_unit_address_if_enabled): /cpus/cpu@9: duplicate unit-address (also used in node /cpus/l2-cache@9)
> > sg2042-cpus.dtsi:466.17-485.5: Warning (unique_unit_address_if_enabled): /cpus/cpu@10: duplicate unit-address (also used in node /cpus/l2-cache@10)
> > sg2042-cpus.dtsi:487.17-506.5: Warning (unique_unit_address_if_enabled): /cpus/cpu@11: duplicate unit-address (also used in node /cpus/l2-cache@11)
> > sg2042-cpus.dtsi:508.17-527.5: Warning (unique_unit_address_if_enabled): /cpus/cpu@12: duplicate unit-address (also used in node /cpus/l2-cache@12)
> > sg2042-cpus.dtsi:529.17-548.5: Warning (unique_unit_address_if_enabled): /cpus/cpu@13: duplicate unit-address (also used in node /cpus/l2-cache@13)
> > sg2042-cpus.dtsi:550.17-569.5: Warning (unique_unit_address_if_enabled): /cpus/cpu@14: duplicate unit-address (also used in node /cpus/l2-cache@14)
> > sg2042-cpus.dtsi:571.17-590.5: Warning (unique_unit_address_if_enabled): /cpus/cpu@15: duplicate unit-address (also used in node /cpus/l2-cache@15)
> >
> > Thanks,
> > Conor.
> 
> I find the rootcause is due to following code in DTS:
> ```
>                 l2_cache0: l2-cache@0 {
>                         compatible = "cache";
>                         cache-block-size = <64>;
>                         cache-level = <2>;
>                         cache-size = <1048576>;
>                         cache-sets = <1024>;
>                         cache-unified;
>                 };
> ```
> To differ 16 l2-cache controller, we add <unit-address>, but due to
> the l2-cache controller on sg2042 has no address, no reg property is
> added here. That's why dtbs_check warns "node has a unit name, but no
> reg or ranges property". I just double-confirmed with sophgo
> engineers, they  told me there is really no address for the cache
> controller for sg2042.
> 
> One solution I use here is to provide unique name for the l2-cache
> node. I learn this from  "arch/arm64/boot/dts/hisilicon/hi3660.dtsi"
> and seems this work and pass dtbs_check with W=1. For example:
> ```
>                 l2_cache0: l2-cache0 {
>                         compatible = "cache";
>                         cache-block-size = <64>;
>                         cache-level = <2>;
>                         cache-size = <1048576>;
>                         cache-sets = <1024>;
>                         cache-unified;
>                 };
> 
>                 l2_cache1: l2-cache1 {
>                         compatible = "cache";
>                         cache-block-size = <64>;
>                         cache-level = <2>;
>                         cache-size = <1048576>;
>                         cache-sets = <1024>;
>                         cache-unified;
>                 };
>                 ......
> ```
> But I remember as mentioned in
> https://devicetree-specification.readthedocs.io/en/latest/chapter2-devicetree-basics.html#generic-names-recommendation,
> node names should be generic. So I have two questions here:
> - Should I use "cache-controller" instead of "l2-cache", though I see
> "l2-cache" is used in many places but not listed in
> devicetree-specification.
> - Even if I replace "l2-cache" with "cache-controller", I think
> "cache-controller0", "cache-controller1" ... are not generic name, but
> due to sg2042 does not have address for cache controller, how to
> handle this problem?

I would go for "cache-controller-0" "cache-controller-1". Close as
possible to the generic node name while having the required differences
between nodes. There's already some examples in-tree (eg renesas) that
do this.

Thanks,
Conor.
  

Regards,

unicornx

Conor Dooley <conor@kernel.org> 于2023年9月22日周五 18:50写道：
>
> On Fri, Sep 22, 2023 at 06:24:25PM +0800, Chen Wang wrote:
> > Regards,
> >
> > unicornx
> >
> > Conor Dooley <conor.dooley@microchip.com> 于2023年9月20日周三 18:01写道：
> > >
> > > On Wed, Sep 20, 2023 at 02:33:48PM +0800, Chen Wang wrote:
> > > > Milk-V Pioneer [1] is a developer motherboard based on SOPHON SG2042 [2]
> > > > in a standard mATX form factor. Add minimal device
> > > > tree files for the SG2042 SOC and the Milk-V Pioneer board.
> > >
> > > Please run dtbs_check with W=1 set & fix the below issues:
> > >
> > > sg2042-cpus.dtsi:1600.25-1607.5: Warning (unit_address_vs_reg): /cpus/l2-cache@0: node has a unit name, but no reg or ranges property
> > > sg2042-cpus.dtsi:1609.25-1616.5: Warning (unit_address_vs_reg): /cpus/l2-cache@1: node has a unit name, but no reg or ranges property
> > > sg2042-cpus.dtsi:1618.25-1625.5: Warning (unit_address_vs_reg): /cpus/l2-cache@2: node has a unit name, but no reg or ranges property
> > > sg2042-cpus.dtsi:1627.25-1634.5: Warning (unit_address_vs_reg): /cpus/l2-cache@3: node has a unit name, but no reg or ranges property
> > > sg2042-cpus.dtsi:1636.25-1643.5: Warning (unit_address_vs_reg): /cpus/l2-cache@4: node has a unit name, but no reg or ranges property
> > > sg2042-cpus.dtsi:1645.25-1652.5: Warning (unit_address_vs_reg): /cpus/l2-cache@5: node has a unit name, but no reg or ranges property
> > > sg2042-cpus.dtsi:1654.25-1661.5: Warning (unit_address_vs_reg): /cpus/l2-cache@6: node has a unit name, but no reg or ranges property
> > > sg2042-cpus.dtsi:1663.25-1670.5: Warning (unit_address_vs_reg): /cpus/l2-cache@7: node has a unit name, but no reg or ranges property
> > > sg2042-cpus.dtsi:1672.25-1679.5: Warning (unit_address_vs_reg): /cpus/l2-cache@8: node has a unit name, but no reg or ranges property
> > > sg2042-cpus.dtsi:1681.25-1688.5: Warning (unit_address_vs_reg): /cpus/l2-cache@9: node has a unit name, but no reg or ranges property
> > > sg2042-cpus.dtsi:1690.27-1697.5: Warning (unit_address_vs_reg): /cpus/l2-cache@10: node has a unit name, but no reg or ranges property
> > > sg2042-cpus.dtsi:1699.27-1706.5: Warning (unit_address_vs_reg): /cpus/l2-cache@11: node has a unit name, but no reg or ranges property
> > > sg2042-cpus.dtsi:1708.27-1715.5: Warning (unit_address_vs_reg): /cpus/l2-cache@12: node has a unit name, but no reg or ranges property
> > > sg2042-cpus.dtsi:1717.27-1724.5: Warning (unit_address_vs_reg): /cpus/l2-cache@13: node has a unit name, but no reg or ranges property
> > > sg2042-cpus.dtsi:1726.27-1733.5: Warning (unit_address_vs_reg): /cpus/l2-cache@14: node has a unit name, but no reg or ranges property
> > > sg2042-cpus.dtsi:1735.27-1742.5: Warning (unit_address_vs_reg): /cpus/l2-cache@15: node has a unit name, but no reg or ranges property
> > > sg2042-cpus.dtsi:256.15-275.5: Warning (unique_unit_address_if_enabled): /cpus/cpu@0: duplicate unit-address (also used in node /cpus/l2-cache@0)
> > > sg2042-cpus.dtsi:277.15-296.5: Warning (unique_unit_address_if_enabled): /cpus/cpu@1: duplicate unit-address (also used in node /cpus/l2-cache@1)
> > > sg2042-cpus.dtsi:298.15-317.5: Warning (unique_unit_address_if_enabled): /cpus/cpu@2: duplicate unit-address (also used in node /cpus/l2-cache@2)
> > > sg2042-cpus.dtsi:319.15-338.5: Warning (unique_unit_address_if_enabled): /cpus/cpu@3: duplicate unit-address (also used in node /cpus/l2-cache@3)
> > > sg2042-cpus.dtsi:340.15-359.5: Warning (unique_unit_address_if_enabled): /cpus/cpu@4: duplicate unit-address (also used in node /cpus/l2-cache@4)
> > > sg2042-cpus.dtsi:361.15-380.5: Warning (unique_unit_address_if_enabled): /cpus/cpu@5: duplicate unit-address (also used in node /cpus/l2-cache@5)
> > > sg2042-cpus.dtsi:382.15-401.5: Warning (unique_unit_address_if_enabled): /cpus/cpu@6: duplicate unit-address (also used in node /cpus/l2-cache@6)
> > > sg2042-cpus.dtsi:403.15-422.5: Warning (unique_unit_address_if_enabled): /cpus/cpu@7: duplicate unit-address (also used in node /cpus/l2-cache@7)
> > > sg2042-cpus.dtsi:424.15-443.5: Warning (unique_unit_address_if_enabled): /cpus/cpu@8: duplicate unit-address (also used in node /cpus/l2-cache@8)
> > > sg2042-cpus.dtsi:445.15-464.5: Warning (unique_unit_address_if_enabled): /cpus/cpu@9: duplicate unit-address (also used in node /cpus/l2-cache@9)
> > > sg2042-cpus.dtsi:466.17-485.5: Warning (unique_unit_address_if_enabled): /cpus/cpu@10: duplicate unit-address (also used in node /cpus/l2-cache@10)
> > > sg2042-cpus.dtsi:487.17-506.5: Warning (unique_unit_address_if_enabled): /cpus/cpu@11: duplicate unit-address (also used in node /cpus/l2-cache@11)
> > > sg2042-cpus.dtsi:508.17-527.5: Warning (unique_unit_address_if_enabled): /cpus/cpu@12: duplicate unit-address (also used in node /cpus/l2-cache@12)
> > > sg2042-cpus.dtsi:529.17-548.5: Warning (unique_unit_address_if_enabled): /cpus/cpu@13: duplicate unit-address (also used in node /cpus/l2-cache@13)
> > > sg2042-cpus.dtsi:550.17-569.5: Warning (unique_unit_address_if_enabled): /cpus/cpu@14: duplicate unit-address (also used in node /cpus/l2-cache@14)
> > > sg2042-cpus.dtsi:571.17-590.5: Warning (unique_unit_address_if_enabled): /cpus/cpu@15: duplicate unit-address (also used in node /cpus/l2-cache@15)
> > >
> > > Thanks,
> > > Conor.
> >
> > I find the rootcause is due to following code in DTS:
> > ```
> >                 l2_cache0: l2-cache@0 {
> >                         compatible = "cache";
> >                         cache-block-size = <64>;
> >                         cache-level = <2>;
> >                         cache-size = <1048576>;
> >                         cache-sets = <1024>;
> >                         cache-unified;
> >                 };
> > ```
> > To differ 16 l2-cache controller, we add <unit-address>, but due to
> > the l2-cache controller on sg2042 has no address, no reg property is
> > added here. That's why dtbs_check warns "node has a unit name, but no
> > reg or ranges property". I just double-confirmed with sophgo
> > engineers, they  told me there is really no address for the cache
> > controller for sg2042.
> >
> > One solution I use here is to provide unique name for the l2-cache
> > node. I learn this from  "arch/arm64/boot/dts/hisilicon/hi3660.dtsi"
> > and seems this work and pass dtbs_check with W=1. For example:
> > ```
> >                 l2_cache0: l2-cache0 {
> >                         compatible = "cache";
> >                         cache-block-size = <64>;
> >                         cache-level = <2>;
> >                         cache-size = <1048576>;
> >                         cache-sets = <1024>;
> >                         cache-unified;
> >                 };
> >
> >                 l2_cache1: l2-cache1 {
> >                         compatible = "cache";
> >                         cache-block-size = <64>;
> >                         cache-level = <2>;
> >                         cache-size = <1048576>;
> >                         cache-sets = <1024>;
> >                         cache-unified;
> >                 };
> >                 ......
> > ```
> > But I remember as mentioned in
> > https://devicetree-specification.readthedocs.io/en/latest/chapter2-devicetree-basics.html#generic-names-recommendation,
> > node names should be generic. So I have two questions here:
> > - Should I use "cache-controller" instead of "l2-cache", though I see
> > "l2-cache" is used in many places but not listed in
> > devicetree-specification.
> > - Even if I replace "l2-cache" with "cache-controller", I think
> > "cache-controller0", "cache-controller1" ... are not generic name, but
> > due to sg2042 does not have address for cache controller, how to
> > handle this problem?
>
> I would go for "cache-controller-0" "cache-controller-1". Close as
> possible to the generic node name while having the required differences
> between nodes. There's already some examples in-tree (eg renesas) that
> do this.
>
> Thanks,
> Conor.

Got, thanks.
  

Palmer Dabbelt <palmer@dabbelt.com> 于2023年9月20日周三 23:22写道：
>
> On Tue, 19 Sep 2023 23:33:48 PDT (-0700), unicornxw@gmail.com wrote:
> > Milk-V Pioneer [1] is a developer motherboard based on SOPHON SG2042 [2]
> > in a standard mATX form factor. Add minimal device
> > tree files for the SG2042 SOC and the Milk-V Pioneer board.
> >
> > Now only support basic uart drivers to boot up into a basic console.
> >
> > Thanks,
> > Chen
> >
> > ---
> >
> > Changes in v2:
> >   The patch series is based on v6.6-rc1. You can simply review or test
> >   the patches at the link [4].
> >   - Improve format for comment of commitments as per input from last review.
> >   - Improve format of DTS as per input from last review.
> >   - Remove numa related stuff from DTS. This part is just for optimization, may
> >     add it later if really needed.
> >
> > Previous versions:
> > v1: due to it is not sent in thread, I have listed permlinks of the patchset
> >     [v1-0/12] ~ [v1-12/12] here for quick reference. You can simply review or
> >     test the patches at the link [3].
> >
> > [1]: https://milkv.io/pioneer
> > [2]: https://en.sophgo.com/product/introduce/sg2042.html
> > [3]: https://github.com/unicornx/linux-riscv/commits/milkv-pioneer-minimal
> > [4]: https://github.com/unicornx/linux-riscv/commits/milkv-pioneer-minimal-v2
> > [v1-0/12]:https://lore.kernel.org/linux-riscv/20230915070856.117514-1-wangchen20@iscas.ac.cn/
> > [v1-1/12]:https://lore.kernel.org/linux-riscv/20230915071005.117575-1-wangchen20@iscas.ac.cn/
> > [v1-2/12]:https://lore.kernel.org/linux-riscv/20230915071409.117692-1-wangchen20@iscas.ac.cn/
> > [v1-3/12]:https://lore.kernel.org/linux-riscv/20230915072242.117935-1-wangchen20@iscas.ac.cn/
> > [v1-4/12]:https://lore.kernel.org/linux-riscv/20230915072333.117991-1-wangchen20@iscas.ac.cn/
> > [v1-5/12]:https://lore.kernel.org/linux-riscv/20230915072358.118045-1-wangchen20@iscas.ac.cn/
> > [v1-6/12]:https://lore.kernel.org/linux-riscv/20230915072415.118100-1-wangchen20@iscas.ac.cn/
> > [v1-7/12]:https://lore.kernel.org/linux-riscv/20230915072431.118154-1-wangchen20@iscas.ac.cn/
> > [v1-8/12]:https://lore.kernel.org/linux-riscv/20230915072451.118209-1-wangchen20@iscas.ac.cn/
> > [v1-9/12]:https://lore.kernel.org/linux-riscv/20230915072517.118266-1-wangchen20@iscas.ac.cn/
> > [v1-10/12]:https://lore.kernel.org/linux-riscv/20230915072558.118325-1-wangchen20@iscas.ac.cn/
> > [v1-11/12]:https://lore.kernel.org/linux-riscv/20230915072624.118388-1-wangchen20@iscas.ac.cn/
> > [v1-12/12]:https://lore.kernel.org/linux-riscv/20230915072653.118448-1-wangchen20@iscas.ac.cn/
> >
> > ---
> >
> > Chen Wang (8):
> >   riscv: Add SOPHGO SOC family Kconfig support
> >   dt-bindings: vendor-prefixes: add milkv/sophgo
> >   dt-bindings: riscv: add sophgo sg2042 bindings
> >   dt-bindings: riscv: Add T-HEAD C920 compatibles
> >   dt-bindings: interrupt-controller: Add SOPHGO's SG2042 PLIC
> >   riscv: dts: add initial SOPHGO SG2042 SoC device tree
> >   riscv: dts: sophgo: add Milk-V Pioneer board device tree
> >   riscv: defconfig: enable SOPHGO SoC
> >
> > Emil Renner Berthing (2):
> >   dt-bindings: serial: snps-dw-apb-uart: Add Sophgo SG2042 uarts
> >   serial: 8250_dw: Add Sophgo SG2042 support
> >
> > Inochi Amaoto (1):
> >   dt-bindings: timer: Add Sophgo sg2042 clint
> >
> >  .../sifive,plic-1.0.0.yaml                    |    1 +
> >  .../devicetree/bindings/riscv/cpus.yaml       |    1 +
> >  .../devicetree/bindings/riscv/sophgo.yaml     |   28 +
> >  .../bindings/serial/snps-dw-apb-uart.yaml     |    1 +
> >  .../bindings/timer/sifive,clint.yaml          |    8 +
> >  .../devicetree/bindings/vendor-prefixes.yaml  |    4 +
> >  MAINTAINERS                                   |    7 +
> >  arch/riscv/Kconfig.socs                       |    5 +
> >  arch/riscv/boot/dts/Makefile                  |    1 +
> >  arch/riscv/boot/dts/sophgo/Makefile           |    3 +
> >  arch/riscv/boot/dts/sophgo/sg2042-cpus.dtsi   | 1744 +++++++++++++++++
> >  .../boot/dts/sophgo/sg2042-milkv-pioneer.dts  |   19 +
> >  arch/riscv/boot/dts/sophgo/sg2042.dtsi        |  439 +++++
> >  arch/riscv/configs/defconfig                  |    1 +
> >  drivers/tty/serial/8250/8250_dw.c             |    5 +-
> >  15 files changed, 2265 insertions(+), 2 deletions(-)
> >  create mode 100644 Documentation/devicetree/bindings/riscv/sophgo.yaml
> >  create mode 100644 arch/riscv/boot/dts/sophgo/Makefile
> >  create mode 100644 arch/riscv/boot/dts/sophgo/sg2042-cpus.dtsi
> >  create mode 100644 arch/riscv/boot/dts/sophgo/sg2042-milkv-pioneer.dts
> >  create mode 100644 arch/riscv/boot/dts/sophgo/sg2042.dtsi
>
> Given this is the first sg2042 and it appears to have a few errata (the
> FP rounding issues and the special fence for starvation), I think we
> want to make sure we figure out how to provide that information to
> userspace.
>

Hi, Palmer,
I don't  understand well what's your meaning of "provide that
information to userspace", can you please clarify more?
And for this patchset, do we still lack something else? This patchset
is the first one for sg2042, but I don't see those issues you
mentioned would block it, becasue the target of this first patchset we
just want to make sure the kernel can boot up and work with a uart
console.

Thanks in adv.
Chen


> > base-commit: 0bb80ecc33a8fb5a682236443c1e740d5c917d1d