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[2620:137:e000::1:20]) by mx.google.com with ESMTP id gf18-20020a170906e21200b0098aa2c42095si5561867ejb.196.2023.06.28.03.57.19; Wed, 28 Jun 2023 03:57:44 -0700 (PDT) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) client-ip=2620:137:e000::1:20; Authentication-Results: mx.google.com; dkim=pass header.i=@quicinc.com header.s=qcppdkim1 header.b=UwET1pWH; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=quicinc.com Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231462AbjF1K0x (ORCPT + 99 others); Wed, 28 Jun 2023 06:26:53 -0400 Received: from mx0a-0031df01.pphosted.com ([205.220.168.131]:21882 "EHLO mx0a-0031df01.pphosted.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S231452AbjF1KYr (ORCPT ); Wed, 28 Jun 2023 06:24:47 -0400 Received: from pps.filterd (m0279866.ppops.net [127.0.0.1]) by mx0a-0031df01.pphosted.com (8.17.1.19/8.17.1.19) with ESMTP id 35S6Vo8F030116; Wed, 28 Jun 2023 10:24:20 GMT DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=quicinc.com; h=from : to : cc : subject : date : message-id : mime-version : content-type; s=qcppdkim1; bh=manEkdmuQleWrH5nEtrGiAPiHViuQZPLn2Zbplf0WL0=; b=UwET1pWHAvI0FGiMTI6UH4ClvuPwn4W80jxaEugB7gorh4Hngr2NNwGdvilR7it6PaUt 2cdkqOi7trG6AeEGzDws15GLDW5af3oEZog2EyX416pWGlWSl5fV2mV4PwrKH7IwSkWi KpKKNZgYg9NO8vc8waRpnnj34JDZ+2HD6RmuLfrmx8pThuNHbCJCPGTitaV+qJbikbL0 o2Ua64DJpwQJ2rrzDKh5gCl64u1iJSiYrV8+UDH9AUWMS9L91hvOtllSeEEQzUPM8dsO tHC+qKJ5YJDatek0efe1RxQ/kfPqAfFWAcyPvYG4aP5JFH9mltC1pL5c7XyFffjNEqnR WA== Received: from nalasppmta05.qualcomm.com (Global_NAT1.qualcomm.com [129.46.96.20]) by mx0a-0031df01.pphosted.com (PPS) with ESMTPS id 3rgfp3rfwf-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Wed, 28 Jun 2023 10:24:20 +0000 Received: from nalasex01a.na.qualcomm.com (nalasex01a.na.qualcomm.com [10.47.209.196]) by NALASPPMTA05.qualcomm.com (8.17.1.5/8.17.1.5) with ESMTPS id 35SANwae027678 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Wed, 28 Jun 2023 10:23:58 GMT Received: from hu-schowdhu-blr.qualcomm.com (10.80.80.8) by nalasex01a.na.qualcomm.com (10.47.209.196) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1118.7; Wed, 28 Jun 2023 03:23:53 -0700 From: Souradeep Chowdhury To: Andy Gross , Konrad Dybcio , Krzysztof Kozlowski , Bjorn Andersson , Rob Herring , Alex Elder , Arnd Bergmann , Greg Kroah-Hartman CC: , , , , Sibi Sankar , Rajendra Nayak , Souradeep Chowdhury Subject: [PATCH V25 0/3] misc: Add driver support for Data Capture and Compare unit(DCC) Date: Wed, 28 Jun 2023 15:53:29 +0530 Message-ID: X-Mailer: git-send-email 2.17.1 MIME-Version: 1.0 X-Originating-IP: [10.80.80.8] X-ClientProxiedBy: nasanex01b.na.qualcomm.com (10.46.141.250) To nalasex01a.na.qualcomm.com (10.47.209.196) X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-GUID: 5ZPY7U27_1T2anr0FKmTSqdNINU2tGcP X-Proofpoint-ORIG-GUID: 5ZPY7U27_1T2anr0FKmTSqdNINU2tGcP X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.254,Aquarius:18.0.957,Hydra:6.0.591,FMLib:17.11.176.26 definitions=2023-06-28_06,2023-06-27_01,2023-05-22_02 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 adultscore=0 mlxlogscore=999 clxscore=1015 suspectscore=0 bulkscore=0 malwarescore=0 impostorscore=0 phishscore=0 lowpriorityscore=0 priorityscore=1501 mlxscore=0 spamscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.12.0-2305260000 definitions=main-2306280091 Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1769943716734168683?= X-GMAIL-MSGID: =?utf-8?q?1769943716734168683?= DCC(Data Capture and Compare) is a DMA engine designed for debugging purposes. In case of a system crash or manual software triggers by the user the DCC hardware stores the value at the register addresses which can be used for debugging purposes. The DCC driver provides the user with debugfs interface to configure the register addresses. The options that the DCC hardware provides include reading from registers, writing to registers, first reading and then writing to registers and looping through the values of the same register. In certain cases a register write needs to be executed for accessing the rest of the registers, also the user might want to record the changing values of a register with time for which he has the option to use the loop feature. The options mentioned above are exposed to the user by debugfs files once the driver is probed. The details and usage of this debugfs files are documented in Documentation/ABI/testing/debugfs-driver-dcc. As an example let us consider a couple of debug scenarios where DCC has been proved to be effective for debugging purposes:- i)TimeStamp Related Issue On SC7180, there was a coresight timestamp issue where it would occasionally be all 0 instead of proper timestamp values. Proper timestamp: Idx:3373; ID:10; I_TIMESTAMP : Timestamp.; Updated val = 0x13004d8f5b7aa; CC=0x9e Zero timestamp: Idx:3387; ID:10; I_TIMESTAMP : Timestamp.; Updated val = 0x0; CC=0xa2 Now this is a non-fatal issue and doesn't need a system reset, but still needs to be rootcaused and fixed for those who do care about coresight etm traces. Since this is a timestamp issue, we would be looking for any timestamp related clocks and such. We get all the clk register details from IP documentation and configure it via DCC config_read debugfs node. Before that we set the current linked list. /* Program the linked list with the addresses */ echo R 0x10c004 > /sys/kernel/debug/qcom-dcc/../3/config echo R 0x10c008 > /sys/kernel/debug/qcom-dcc/../3/config echo R 0x10c00c > /sys/kernel/debug/qcom-dcc/../3/config echo R 0x10c010 > /sys/kernel/debug/qcom-dcc/../3/config ..... and so on for other timestamp related clk registers /* Other way of specifying is in "addr len" pair, in below case it specifies to capture 4 words starting 0x10C004 */ echo R 0x10C004 4 > /sys/kernel/debug/qcom-dcc/../3/config_read /* Enable DCC */ echo 1 > /sys/kernel/debug/qcom-dcc/../3/enable /* Run the timestamp test for working case */ /* Send SW trigger */ echo 1 > /sys/kernel/debug/qcom-dcc/../trigger /* Read SRAM */ cat /dev/dcc_sram > dcc_sram1.bin /* Run the timestamp test for non-working case */ /* Send SW trigger */ echo 1 > /sys/kernel/debug/qcom-dcc/../trigger /* Read SRAM */ cat /dev/dcc_sram > dcc_sram2.bin Get the parser from [1] and checkout the latest branch. /* Parse the SRAM bin */ python dcc_parser.py -s dcc_sram1.bin --v2 -o output/ python dcc_parser.py -s dcc_sram2.bin --v2 -o output/ Sample parsed output of dcc_sram1.bin: 03/14/21 Linux DCC Parser next_ll_offset : 0x1c ii)NOC register errors A particular class of registers called NOC which are functional registers was reporting errors while logging the values.To trace these errors the DCC has been used effectively. The steps followed were similar to the ones mentioned above. In addition to NOC registers a few other dependent registers were configured in DCC to monitor it's values during a crash. A look at the dependent register values revealed that the crash was happening due to a secured access to one of these dependent registers. All these debugging activity and finding the root cause was achieved using DCC. DCC parser is available at the following open source location https://git.codelinaro.org/clo/le/platform/vendor/qcom-opensource/tools/-/tree/opensource-tools.lnx.1.0.r176-rel/dcc_parser Changes in v25 * Updated the documentation of the structure dcc_config_entry as per the comments in V23 * Updated the documentation of the dcc Kconfig definition as per comment in V24 * Used u64 where applicable * Removed the mutex locks where it is not needed * Removed the use of unlikely keyword * Renamed "nr_link_list" to "max_link_list" Souradeep Chowdhury (3): dt-bindings: misc: qcom,dcc: Add the dtschema misc: dcc: Add driver support for Data Capture and Compare unit(DCC) MAINTAINERS: Add the entry for DCC(Data Capture and Compare) driver support Documentation/ABI/testing/debugfs-driver-dcc | 10 +- .../devicetree/bindings/misc/qcom,dcc.yaml | 44 + MAINTAINERS | 8 + drivers/misc/Kconfig | 8 + drivers/misc/Makefile | 1 + drivers/misc/qcom-dcc.c | 1312 +++++++++++++++++ 6 files changed, 1378 insertions(+), 5 deletions(-) create mode 100644 Documentation/devicetree/bindings/misc/qcom,dcc.yaml create mode 100644 drivers/misc/qcom-dcc.c