mbox series

[V24,0/3] misc: Add driver support for Data Capture and Compare unit(DCC)

Message ID cover.1687855361.git.quic_schowdhu@quicinc.com
Headers
Series misc: Add driver support for Data Capture and Compare unit(DCC) |

Message

Souradeep Chowdhury June 27, 2023, 9:49 a.m. UTC 
  DCC(Data Capture and Compare) is a DMA engine designed for debugging purposes.
In case of a system crash or manual software triggers by the user the DCC hardware
stores the value at the register addresses which can be used for debugging purposes.
The DCC driver provides the user with debugfs interface to configure the register
addresses. The options that the DCC hardware provides include reading from registers,
writing to registers, first reading and then writing to registers and looping
through the values of the same register.

In certain cases a register write needs to be executed for accessing the rest of the
registers, also the user might want to record the changing values of a register with
time for which he has the option to use the loop feature.

The options mentioned above are exposed to the user by debugfs files once the driver
is probed. The details and usage of this debugfs files are documented in
Documentation/ABI/testing/debugfs-driver-dcc.

As an example let us consider a couple of debug scenarios where DCC has been proved to be
effective for debugging purposes:-

i)TimeStamp Related Issue

On SC7180, there was a coresight timestamp issue where it would occasionally be all 0
instead of proper timestamp values.

Proper timestamp:
Idx:3373; ID:10; I_TIMESTAMP : Timestamp.; Updated val = 0x13004d8f5b7aa; CC=0x9e

Zero timestamp:
Idx:3387; ID:10; I_TIMESTAMP : Timestamp.; Updated val = 0x0; CC=0xa2

Now this is a non-fatal issue and doesn't need a system reset, but still needs
to be rootcaused and fixed for those who do care about coresight etm traces.
Since this is a timestamp issue, we would be looking for any timestamp related
clocks and such.

We get all the clk register details from IP documentation and configure it
via DCC config_read debugfs node. Before that we set the current linked list.

/* Program the linked list with the addresses */
echo R 0x10c004 > /sys/kernel/debug/qcom-dcc/../3/config
echo R 0x10c008 > /sys/kernel/debug/qcom-dcc/../3/config
echo R 0x10c00c > /sys/kernel/debug/qcom-dcc/../3/config
echo R 0x10c010 > /sys/kernel/debug/qcom-dcc/../3/config
..... and so on for other timestamp related clk registers

/* Other way of specifying is in "addr len" pair, in below case it
specifies to capture 4 words starting 0x10C004 */

echo R 0x10C004 4 > /sys/kernel/debug/qcom-dcc/../3/config_read

/* Enable DCC */
echo 1 > /sys/kernel/debug/qcom-dcc/../3/enable

/* Run the timestamp test for working case */

/* Send SW trigger */
echo 1 > /sys/kernel/debug/qcom-dcc/../trigger

/* Read SRAM */
cat /dev/dcc_sram > dcc_sram1.bin

/* Run the timestamp test for non-working case */

/* Send SW trigger */
echo 1 > /sys/kernel/debug/qcom-dcc/../trigger

/* Read SRAM */
cat /dev/dcc_sram > dcc_sram2.bin

Get the parser from [1] and checkout the latest branch.

/* Parse the SRAM bin */
python dcc_parser.py -s dcc_sram1.bin --v2 -o output/
python dcc_parser.py -s dcc_sram2.bin --v2 -o output/

Sample parsed output of dcc_sram1.bin:

<hwioDump version="1">
         <timestamp>03/14/21</timestamp>
             <generator>Linux DCC Parser</generator>
                 <chip name="None" version="None">
                 <register address="0x0010c004" value="0x80000000" />
                 <register address="0x0010c008" value="0x00000008" />
                 <register address="0x0010c00c" value="0x80004220" />
                 <register address="0x0010c010" value="0x80000000" />
             </chip>
     <next_ll_offset>next_ll_offset : 0x1c </next_ll_offset>
</hwioDump>

ii)NOC register errors

A particular class of registers called NOC which are functional registers was reporting
errors while logging the values.To trace these errors the DCC has been used effectively.
The steps followed were similar to the ones mentioned above.
In addition to NOC registers a few other dependent registers were configured in DCC to
monitor it's values during a crash. A look at the dependent register values revealed that
the crash was happening due to a secured access to one of these dependent registers.
All these debugging activity and finding the root cause was achieved using DCC.

DCC parser is available at the following open source location

https://git.codelinaro.org/clo/le/platform/vendor/qcom-opensource/tools/-/tree/opensource-tools.lnx.1.0.r176-rel/dcc_parser

Changes in v24

*Implemented the comments in v23

Souradeep Chowdhury (3):
  dt-bindings: misc: qcom,dcc: Add the dtschema
  misc: dcc: Add driver support for Data Capture and Compare unit(DCC)
  MAINTAINERS: Add the entry for DCC(Data Capture and Compare) driver
    support

 Documentation/ABI/testing/debugfs-driver-dcc  |   10 +-
 .../devicetree/bindings/misc/qcom,dcc.yaml    |   44 +
 MAINTAINERS                                   |    8 +
 drivers/misc/Kconfig                          |    9 +
 drivers/misc/Makefile                         |    1 +
 drivers/misc/qcom-dcc.c                       | 1316 +++++++++++++++++
 6 files changed, 1383 insertions(+), 5 deletions(-)
 create mode 100644 Documentation/devicetree/bindings/misc/qcom,dcc.yaml
 create mode 100644 drivers/misc/qcom-dcc.c

--
2.17.1

Comments

Greg KH June 27, 2023, 10:22 a.m. UTC | #1 
On Tue, Jun 27, 2023 at 03:19:23PM +0530, Souradeep Chowdhury wrote:
> Changes in v24
> 
> *Implemented the comments in v23

That explains absolutely nothing about what changed at all.

What would you do if you got a patch series that had this as a change
list?  What do you expect us to do?

{sigh}
Souradeep Chowdhury June 28, 2023, 5:45 a.m. UTC | #2 
On 6/27/2023 3:52 PM, Greg Kroah-Hartman wrote:
> On Tue, Jun 27, 2023 at 03:19:23PM +0530, Souradeep Chowdhury wrote:
>> Changes in v24
>>
>> *Implemented the comments in v23
> 
> That explains absolutely nothing about what changed at all.
> 
> What would you do if you got a patch series that had this as a change
> list?  What do you expect us to do?
> 
> {sigh}

My apologies on missing out on the specifics.

The main changes in this version are as follows:-

* Updated the documentation of the structure dcc_config_entry
* Renamed "nr_link_list" to "max_link_list"
* Used u64 where applicable
* Removed the locks from ready_read method and also dropped
   the use of unlikely keyword.

>
Greg KH June 28, 2023, 6:41 a.m. UTC | #3 
On Wed, Jun 28, 2023 at 11:15:46AM +0530, Souradeep Chowdhury wrote:
> 
> 
> On 6/27/2023 3:52 PM, Greg Kroah-Hartman wrote:
> > On Tue, Jun 27, 2023 at 03:19:23PM +0530, Souradeep Chowdhury wrote:
> > > Changes in v24
> > > 
> > > *Implemented the comments in v23
> > 
> > That explains absolutely nothing about what changed at all.
> > 
> > What would you do if you got a patch series that had this as a change
> > list?  What do you expect us to do?
> > 
> > {sigh}
> 
> My apologies on missing out on the specifics.
> 
> The main changes in this version are as follows:-
> 
> * Updated the documentation of the structure dcc_config_entry
> * Renamed "nr_link_list" to "max_link_list"
> * Used u64 where applicable
> * Removed the locks from ready_read method and also dropped
>   the use of unlikely keyword.

Please fix this up and send a new version.

thanks,

greg k-h