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[2620:137:e000::1:20]) by mx.google.com with ESMTP id s25-20020a63af59000000b00530b6228f91si1865029pgo.895.2023.06.08.19.07.54; Thu, 08 Jun 2023 19:08:08 -0700 (PDT) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) client-ip=2620:137:e000::1:20; Authentication-Results: mx.google.com; dkim=fail header.i=@intel.com header.s=Intel header.b=ZhmJ0RpB; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=intel.com Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S234442AbjFICGP (ORCPT + 99 others); Thu, 8 Jun 2023 22:06:15 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:59150 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229784AbjFICGN (ORCPT ); Thu, 8 Jun 2023 22:06:13 -0400 Received: from mga09.intel.com (mga09.intel.com [134.134.136.24]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id C7BED30D2; Thu, 8 Jun 2023 19:06:12 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1686276372; x=1717812372; h=from:to:cc:subject:date:message-id:mime-version: content-transfer-encoding; bh=yf/goSKZB9+Tho1Vqu1nbwxS6JRsN/UDlhFgsPkydz8=; b=ZhmJ0RpBdfrMKU0SYtsaNKZzlruL/A5A6ghA6LspeOKIT5hlzAaPvjdh p7RMu69C4IU1ot6Kf/MQ1atO+XVbThWjXKNKnSgRUrSOsdNRVBrobKjXK v6kOl4ajIM/jJGXe9aBasgBHlS4UQRJFDJ512L7FeVX0QeKM4gMkk1p87 rce5FHWXZE1zjy2vj3mhuscF7nrGUTvSD+e9D+FMM22X7WL8PG2zwwpTa KM8f3bCCmL59mbhKD73CDDrUrrTI3mYKy2UkJseT2ToV+Xct81C6P7NG2 LSoOA/h3LbbUhYe0HWRIXjHvble5+7uTB3drqmws6qv8+v21fJSRLf6Zm Q==; X-IronPort-AV: E=McAfee;i="6600,9927,10735"; a="359975109" X-IronPort-AV: E=Sophos;i="6.00,228,1681196400"; d="scan'208";a="359975109" Received: from fmsmga007.fm.intel.com ([10.253.24.52]) by orsmga102.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 08 Jun 2023 19:06:12 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6600,9927,10735"; a="713334272" X-IronPort-AV: E=Sophos;i="6.00,228,1681196400"; d="scan'208";a="713334272" Received: from haibo-optiplex-7090.sh.intel.com ([10.239.159.132]) by fmsmga007-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 08 Jun 2023 19:06:05 -0700 From: Haibo Xu Cc: xiaobo55x@gmail.com, haibo1.xu@intel.com, ajones@ventanamicro.com, maz@kernel.org, oliver.upton@linux.dev, seanjc@google.com, Paolo Bonzini , Jonathan Corbet , Anup Patel , Atish Patra , Paul Walmsley , Palmer Dabbelt , Albert Ou , Shuah Khan , James Morse , Suzuki K Poulose , Zenghui Yu , David Matlack , Ben Gardon , Vipin Sharma , Colton Lewis , kvm@vger.kernel.org, linux-doc@vger.kernel.org, linux-kernel@vger.kernel.org, kvm-riscv@lists.infradead.org, linux-riscv@lists.infradead.org, linux-kselftest@vger.kernel.org, linux-arm-kernel@lists.infradead.org, kvmarm@lists.linux.dev Subject: [PATCH v3 00/10] RISCV: Add KVM_GET_REG_LIST API Date: Fri, 9 Jun 2023 10:12:08 +0800 Message-Id: X-Mailer: git-send-email 2.34.1 MIME-Version: 1.0 X-Spam-Status: No, score=-4.4 required=5.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,RCVD_IN_DNSWL_MED, RCVD_IN_MSPIKE_H3,RCVD_IN_MSPIKE_WL,SPF_HELO_NONE,SPF_NONE, T_SCC_BODY_TEXT_LINE,URIBL_BLOCKED autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net To: unlisted-recipients:; (no To-header on input) Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1768189055322172899?= X-GMAIL-MSGID: =?utf-8?q?1768189055322172899?= KVM_GET_REG_LIST will dump all register IDs that are available to KVM_GET/SET_ONE_REG and It's very useful to identify some platform regression issue during VM migration. Patch 1-7 re-structured the get-reg-list test in aarch64 to make some of the code as common test framework that can be shared by riscv. Patch 8 enabled the KVM_GET_REG_LIST API in riscv and patch 9-10 added the corresponding kselftest for checking possible register regressions. The get-reg-list kvm selftest was ported from aarch64 and tested with Linux 6.4-rc5 on a Qemu riscv64 virt machine. --- Changed since v2: * Rebase to Linux 6.4-rc5 * Filter out ZICBO* config and ISA_EXT registers report if the extensions were not supported in host * Enable AIA CSR test * Move vCPU extension check_supported() to finalize_vcpu() per Andrew's suggestion * Switch to use KVM_REG_SIZE_ULONG for most registers' definition --- Changed since v1: * rebase to Andrew's changes * fix coding style Andrew Jones (7): KVM: arm64: selftests: Replace str_with_index with strdup_printf KVM: arm64: selftests: Drop SVE cap check in print_reg KVM: arm64: selftests: Remove print_reg's dependency on vcpu_config KVM: arm64: selftests: Rename vcpu_config and add to kvm_util.h KVM: arm64: selftests: Delete core_reg_fixup KVM: arm64: selftests: Split get-reg-list test code KVM: arm64: selftests: Finish generalizing get-reg-list Haibo Xu (3): KVM: riscv: Add KVM_GET_REG_LIST API support KVM: riscv: selftests: Skip some registers set operation KVM: riscv: selftests: Add get-reg-list test Documentation/virt/kvm/api.rst | 2 +- arch/riscv/kvm/vcpu.c | 378 +++++++++++ tools/testing/selftests/kvm/Makefile | 11 +- .../selftests/kvm/aarch64/get-reg-list.c | 540 ++-------------- tools/testing/selftests/kvm/get-reg-list.c | 421 ++++++++++++ .../selftests/kvm/include/kvm_util_base.h | 16 + .../selftests/kvm/include/riscv/processor.h | 3 + .../testing/selftests/kvm/include/test_util.h | 2 + tools/testing/selftests/kvm/lib/test_util.c | 15 + .../selftests/kvm/riscv/get-reg-list.c | 611 ++++++++++++++++++ 10 files changed, 1499 insertions(+), 500 deletions(-) create mode 100644 tools/testing/selftests/kvm/get-reg-list.c create mode 100644 tools/testing/selftests/kvm/riscv/get-reg-list.c