From patchwork Mon Nov 14 20:06:14 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Pawan Gupta X-Patchwork-Id: 1625 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a5d:6687:0:0:0:0:0 with SMTP id l7csp2342709wru; Mon, 14 Nov 2022 12:13:00 -0800 (PST) X-Google-Smtp-Source: AA0mqf58Y9/JInLB2vtpH/ulGptWtSHVnCrO9jT1qmJiH4JP/LYRDVR78ZC7gag1GFW4tRgZaS4v X-Received: by 2002:a17:906:3e90:b0:78a:52bb:d904 with SMTP id a16-20020a1709063e9000b0078a52bbd904mr11148654ejj.630.1668456780683; Mon, 14 Nov 2022 12:13:00 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1668456780; cv=none; d=google.com; s=arc-20160816; b=NZjosooZejCsWIZTqTFeve8aV/Z/FbI/hg0xJp1ba2Utn6psVRWQXjtK8QvdmS6Ayc iHjekh3W5Q3FupIZLvKI3yeW4N9iFXe3Ndj83Vp3qYFGizSnkme7qS8gPAkZKdbX44O5 lE/lpHrYTxYl9Po15k7Phw48JHKK64Je0tWXFevGKExiJrXTNdEBBCgFSpyY7eCMt3Q4 o9hJw235omaah7iS1Sujb6RLd1SnvH3fh0c6V1y7o4l9tHQkmRN81iL5/UrfTEV3DDPB OUU5slsJ1Jp416r2DgDyqKzOtyAz85vn+/Ljtc3sNmt9txIYobiBzMyhuKHidwLSrGrm haow== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :message-id:date:subject:cc:to:from:dkim-signature; bh=m4kduuDA5wqu8E8lQ6reVyylo0KIDqUv9fOZnz50B4k=; b=wQqIz4cIR9YaOxUFxJBfHMqu+evE5qPQJBAfvoC614s5oYlyXlGc7VJuQiwaAU9/xF gt5PGsM4+U/HxD8gJ1pxhXS/jZNntFFJFffJ5wLEJT3HF+zXBlBwfTZqcbFtIEAPYBF0 urM7bS3H7gTIDte5CXQrrwzANG5kj0Dgo7KhFQvxyQNsRLqZhZv7qktNPWB9HI3CuSAB LbWieSH6npHm8gC002SoNG/sypxWugkWsExrq+gbI8We3gbkisObaXquTPUgXEuiWlCo PmtB5eeUF6t+d2HmZI74FG15226qSacl9Z+SDTHm7mY+d4Antmh+U+fvZXwlVE9g44FK T1uQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@intel.com header.s=Intel header.b="BgnAl6/T"; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=intel.com Received: from out1.vger.email (out1.vger.email. [2620:137:e000::1:20]) by mx.google.com with ESMTP id nb4-20020a1709071c8400b007ae2368c8b3si10250148ejc.730.2022.11.14.12.12.35; Mon, 14 Nov 2022 12:13:00 -0800 (PST) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) client-ip=2620:137:e000::1:20; Authentication-Results: mx.google.com; dkim=pass header.i=@intel.com header.s=Intel header.b="BgnAl6/T"; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=intel.com Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S237401AbiKNUG1 (ORCPT + 99 others); Mon, 14 Nov 2022 15:06:27 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:34032 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S235591AbiKNUGY (ORCPT ); Mon, 14 Nov 2022 15:06:24 -0500 Received: from mga04.intel.com (mga04.intel.com [192.55.52.120]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id F1E58B43; Mon, 14 Nov 2022 12:06:22 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1668456383; x=1699992383; h=from:to:cc:subject:date:message-id:mime-version: content-transfer-encoding; bh=Z7vdBH5qB1VYZSaLpKPfeGlUHh3AbGFnYftB56TDl0E=; b=BgnAl6/TZXV9GoMsoicNuRT8TE6MW9Vb9UvlZVwntm2EOfOc3no8uqSq LWm9/ulBTYMFVnbZcEQowLhtY3LMob5L0QQn7/p+fkjnzB/+ykarK7PCD 5QyA8K5xalMsTGLvz2ktCzj3zl4rm1YjXvmWu/4kiIaqXFrg27mqRG3CQ /c85Oeuvbcew1YCRdPw+uWs4EKLB8OppXVJgT6gPDUd4OnUm0MNAUImLj 7IrqdP21C4ieYOyYOxhWL0mlpqUBogTy8g7bbxOoUysD7ODuIZzbKNyzB bK0J9uC/UaPXIIcYukrTWF1oIN1iiJcqRBZ9/MG3Ciy4DCRALVp6EzF8r A==; X-IronPort-AV: E=McAfee;i="6500,9779,10531"; a="310779573" X-IronPort-AV: E=Sophos;i="5.96,164,1665471600"; d="scan'208";a="310779573" Received: from orsmga003.jf.intel.com ([10.7.209.27]) by fmsmga104.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 14 Nov 2022 12:06:22 -0800 X-IronPort-AV: E=McAfee;i="6500,9779,10531"; a="589508113" X-IronPort-AV: E=Sophos;i="5.96,164,1665471600"; d="scan'208";a="589508113" Received: from parandri-mobl.amr.corp.intel.com (HELO guptapa-desk.intel.com) ([10.209.117.50]) by orsmga003-auth.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 14 Nov 2022 12:06:21 -0800 From: Pawan Gupta To: "H. Peter Anvin" , Thomas Gleixner , David.Kaplan@amd.com, thomas.lendacky@amd.com, Borislav Petkov , x86@kernel.org, hdegoede@redhat.com, Dave Hansen , Andrew Cooper , Pavel Machek , Ingo Molnar , "Rafael J. Wysocki" Cc: linux-kernel@vger.kernel.org, linux-pm@vger.kernel.org, Daniel Sneddon , antonio.gomez.iglesias@linux.intel.com Subject: [PATCH v2 0/2] Check enumeration before MSR save/restore Date: Mon, 14 Nov 2022 12:06:14 -0800 Message-Id: X-Mailer: git-send-email 2.37.3 MIME-Version: 1.0 X-Spam-Status: No, score=-3.0 required=5.0 tests=AC_FROM_MANY_DOTS,BAYES_00, DKIMWL_WL_HIGH,DKIM_SIGNED,DKIM_VALID,DKIM_VALID_EF,RCVD_IN_DNSWL_MED, SPF_HELO_NONE,SPF_NONE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1749503737000119085?= X-GMAIL-MSGID: =?utf-8?q?1749503737000119085?= v2: - Dropped patch for X86_FEATURE_AMD64_LS_CFG, using X86_FEATURE_AMD64_LS_CFG_SSBD instead. - Commit message updated. v1: https://lore.kernel.org/lkml/cover.1663025154.git.pawan.kumar.gupta@linux.intel.com/ Hi, This patchset is to fix the "unchecked MSR access error" [1] during S3 resume. Patch 1/3 adds a feature bit for MSR_IA32_TSX_CTRL. Patch 2/3 adds a feature bit for MSR_AMD64_LS_CFG. Patch 3/3 adds check for feature bit before adding any speculation control MSR to the list of MSRs to save/restore. [1] https://lore.kernel.org/lkml/20220906201743.436091-1-hdegoede@redhat.com/ Thanks, Pawan Pawan Gupta (2): x86/tsx: Add feature bit for TSX control MSR support x86/pm: Add enumeration check before spec MSRs save/restore setup arch/x86/include/asm/cpufeatures.h | 1 + arch/x86/kernel/cpu/tsx.c | 30 +++++++++++++++--------------- arch/x86/power/cpu.c | 23 ++++++++++++++++------- 3 files changed, 32 insertions(+), 22 deletions(-)