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[0/2] perf: add T-HEAD C9xx series cpu support

Message ID IA1PR20MB49539201E93DE46A9A2A8E74BB799@IA1PR20MB4953.namprd20.prod.outlook.com
Headers
Series perf: add T-HEAD C9xx series cpu support |

Message

Inochi Amaoto May 16, 2023, 2:37 a.m. UTC 
  The T-HEAD C9xx series cpu is a series of riscv CPU IP. As this IP was
proposed before the current riscv event standard. It has a non-standard
events encoding for perf events and unimplemented MARCH and MIMP CSR.
This patch add these events to support C9xx cpus.

AFAIK, at least the following chips used C9xx cpu.

* Allwinner D1 (C906)
* T-HEAD th1520 (C910)
* Sophgo mango (C920)

Inochi Amaoto (2):
  perf tools riscv: Allow get_cpuid return empty MARCH and MIMP
  perf vendor events riscv: add T-HEAD C9xx JSON file

 tools/perf/arch/riscv/util/header.c           |  7 +-
 tools/perf/pmu-events/arch/riscv/mapfile.csv  |  1 +
 .../arch/riscv/t-head/c9xx/cache.json         | 67 ++++++++++++++++++
 .../arch/riscv/t-head/c9xx/firmware.json      | 68 +++++++++++++++++++
 .../arch/riscv/t-head/c9xx/instruction.json   | 22 ++++++
 .../arch/riscv/t-head/c9xx/microarch.json     | 42 ++++++++++++
 6 files changed, 201 insertions(+), 6 deletions(-)
 create mode 100644 tools/perf/pmu-events/arch/riscv/t-head/c9xx/cache.json
 create mode 100644 tools/perf/pmu-events/arch/riscv/t-head/c9xx/firmware.json
 create mode 100644 tools/perf/pmu-events/arch/riscv/t-head/c9xx/instruction.json
 create mode 100644 tools/perf/pmu-events/arch/riscv/t-head/c9xx/microarch.json

--
2.40.1

Comments

Inochi Amaoto May 16, 2023, 9:42 a.m. UTC | #1 
A minimal example for C910 is as follows, I have test this on a C920 chip.

pmu {
	compatible = "riscv,pmu";
	riscv,event-to-mhpmcounters =
		// event-start event-end a bitmap of all the MHPMCOUNTERx
		<0x00006 0x00006 0x00000400>,
		<0x00005 0x00005 0x00000800>,
		<0x10000 0x10000 0x00004000>,
		<0x10001 0x10001 0x00008000>,
		<0x10002 0x10002 0x00010000>,
		<0x10003 0x10003 0x00020000>,
		<0x10008 0x10008 0x00000008>,
		<0x10009 0x10009 0x00000010>,
		<0x10010 0x10010 0x00040000>,
		<0x10011 0x10011 0x00080000>,
		<0x10012 0x10012 0x00100000>,
		<0x10013 0x10013 0x00200000>,
		<0x10019 0x10019 0x00000040>,
		<0x10021 0x10021 0x00000020>;
	riscv,event-to-mhpmevent =
		// event-id event-selector
		/* mhpmevent3: L1I_READ_ACCESS */
		<0x10008 0x00000000 0x00000001>,
		/* mhpmevent4: L1I_READ_MISS */
		<0x10009 0x00000000 0x00000002>,
		/* mhpmevent5: ITLB_READ_MISS */
		<0x10021 0x00000000 0x00000003>,
		/* mhpmevent6: DTLB_READ_MISS */
		<0x10019 0x00000000 0x00000004>,
		/* mhpmevent10: PMU_HW_BRANCH_MISSES */
		<0x00006 0x00000000 0x00000008>,
		/* mhpmevent11: PMU_HW_BRANCH_INSTRUCTIONS */
		<0x00005 0x00000000 0x00000009>,
		/* mhpmevent14: L1D_READ_ACCESS */
		<0x10000 0x00000000 0x0000000c>,
		/* mhpmevent15: L1D_READ_MISS */
		<0x10001 0x00000000 0x0000000d>,
		/* mhpmevent16: L1D_WRITE_ACCESS */
		<0x10002 0x00000000 0x0000000e>,
		/* mhpmevent17: L1D_WRITE_MISS */
		<0x10003 0x00000000 0x0000000f>,
		/* mhpmevent18: LL_READ_ACCESS */
		<0x10010 0x00000000 0x00000010>,
		/* mhpmevent19: LL_READ_MISS */
		<0x10011 0x00000000 0x00000011>,
		/* mhpmevent20: LL_WRITE_ACCESS */
		<0x10012 0x00000000 0x00000012>,
		/* mhpmevent21: LL_WRITE_MISS */
		<0x10013 0x00000000 0x00000013>;
	riscv,raw-event-to-mhpmcounters =
		/* mhpmevent3: L1 ICache Access Counter */
		<0x00000000 0x00000001 0xffffffff 0xffffffff 0x00000008>,
		/* mhpmevent4: L1 ICache Miss Counter */
		<0x00000000 0x00000002 0xffffffff 0xffffffff 0x00000010>,
		/* mhpmevent5: I-UTLB Miss Counter */
		<0x00000000 0x00000003 0xffffffff 0xffffffff 0x00000020>,
		/* mhpmevent6: D-UTLB Miss Counter */
		<0x00000000 0x00000004 0xffffffff 0xffffffff 0x00000040>,
		/* mhpmevent7: JTLB Miss */
		<0x00000000 0x00000005 0xffffffff 0xffffffff 0x00000080>,
		/* mhpmevent8: Conditional Branch Mispredict */
		<0x00000000 0x00000006 0xffffffff 0xffffffff 0x00000100>,
		/* mhpmevent9: Conditional Branch Instruction Counter */
		/* <0x00000000 0x00000007 0xffffffff 0xffffffff 0x00000200>, */
		/* mhpmevent10: Indirect Branch Mispredict Counter */
		<0x00000000 0x00000008 0xffffffff 0xffffffff 0x00000400>,
		/* mhpmevent11: Indirect Branch Instruction Counter */
		<0x00000000 0x00000009 0xffffffff 0xffffffff 0x00000800>,
		/* mhpmevent12: LSU Spec Fail */
		<0x00000000 0x0000000a 0xffffffff 0xffffffff 0x00001000>,
		/* mhpmevent13: Store Instruction */
		<0x00000000 0x0000000b 0xffffffff 0xffffffff 0x00002000>,
		/* mhpmevent14: L1 DCache read access Counter */
		<0x00000000 0x0000000c 0xffffffff 0xffffffff 0x00004000>,
		/* mhpmevent15: L1 DCache read miss Counter */
		<0x00000000 0x0000000d 0xffffffff 0xffffffff 0x00008000>,
		/* mhpmevent16: L1 DCache write access Counter */
		<0x00000000 0x0000000e 0xffffffff 0xffffffff 0x00010000>,
		/* mhpmevent17: L1 DCache write access Counter */
		<0x00000000 0x0000000f 0xffffffff 0xffffffff 0x00020000>,
		/* mhpmevent18: L2 Cache read access Counter */
		<0x00000000 0x00000010 0xffffffff 0xffffffff 0x00040000>,
		/* mhpmevent19: L2 Cache read miss Counter */
		<0x00000000 0x00000011 0xffffffff 0xffffffff 0x00080000>,
		/* mhpmevent20: L2 Cache write access Counter */
		<0x00000000 0x00000012 0xffffffff 0xffffffff 0x00100000>,
		/* mhpmevent21: L2 Cache write miss Counter */
		<0x00000000 0x00000013 0xffffffff 0xffffffff 0x00200000>,
		/* mhpmevent22: RF Launch Fail */
		<0x00000000 0x00000014 0xffffffff 0xffffffff 0x00400000>,
		/* mhpmevent23: RF Reg Launch Fail */
		<0x00000000 0x00000015 0xffffffff 0xffffffff 0x00800000>,
		/* mhpmevent24: RF Instruction */
		<0x00000000 0x00000016 0xffffffff 0xffffffff 0x01000000>,
		/* mhpmevent25: LSU Cross 4K Stall */
		<0x00000000 0x00000017 0xffffffff 0xffffffff 0x02000000>,
		/* mhpmevent26: LSU Other Stall */
		<0x00000000 0x00000018 0xffffffff 0xffffffff 0x04000000>,
		/* mhpmevent27: LSU SQ Discard */
		<0x00000000 0x00000019 0xffffffff 0xffffffff 0x08000000>,
		/* mhpmevent28: LSU SQ Data Discard */
		<0x00000000 0x0000001a 0xffffffff 0xffffffff 0x10000000>;
};


> Hello Inochi Amaoto!
>
> Thank you for your series!
>
> Could you also provide HPM device tree bindings which were used in
> OpenSBI for testing in cover letter ?
>
> On Tue, 2023-05-16 at 10:37 +0800, Inochi Amaoto wrote:
> > The T-HEAD C9xx series cpu is a series of riscv CPU IP. As this IP
> > was
> > proposed before the current riscv event standard. It has a non-
> > standard
> > events encoding for perf events and unimplemented MARCH and MIMP CSR.
> > This patch add these events to support C9xx cpus.
> >
> > AFAIK, at least the following chips used C9xx cpu.
> >
> > * Allwinner D1 (C906)
> > * T-HEAD th1520 (C910)
> > * Sophgo mango (C920)
> >
> > Inochi Amaoto (2):
> >   perf tools riscv: Allow get_cpuid return empty MARCH and MIMP
> >   perf vendor events riscv: add T-HEAD C9xx JSON file
> >
> >  tools/perf/arch/riscv/util/header.c           |  7 +-
> >  tools/perf/pmu-events/arch/riscv/mapfile.csv  |  1 +
> >  .../arch/riscv/t-head/c9xx/cache.json         | 67
> > ++++++++++++++++++
> >  .../arch/riscv/t-head/c9xx/firmware.json      | 68
> > +++++++++++++++++++
> >  .../arch/riscv/t-head/c9xx/instruction.json   | 22 ++++++
> >  .../arch/riscv/t-head/c9xx/microarch.json     | 42 ++++++++++++
> >  6 files changed, 201 insertions(+), 6 deletions(-)
> >  create mode 100644 tools/perf/pmu-events/arch/riscv/t-
> > head/c9xx/cache.json
> >  create mode 100644 tools/perf/pmu-events/arch/riscv/t-
> > head/c9xx/firmware.json
> >  create mode 100644 tools/perf/pmu-events/arch/riscv/t-
> > head/c9xx/instruction.json
> >  create mode 100644 tools/perf/pmu-events/arch/riscv/t-
> > head/c9xx/microarch.json
> >
> > --
> > 2.40.1
> >
> >
> > _______________________________________________
> > linux-riscv mailing list
> > linux-riscv@lists.infradead.org
> > http://lists.infradead.org/mailman/listinfo/linux-riscv
Nikita Shubin May 16, 2023, 10:32 a.m. UTC | #2 
Hello Inochi Amaoto!

Thank you for your series!

Could you also provide HPM device tree bindings which were used in
OpenSBI for testing in cover letter ?

On Tue, 2023-05-16 at 10:37 +0800, Inochi Amaoto wrote:
> The T-HEAD C9xx series cpu is a series of riscv CPU IP. As this IP
> was
> proposed before the current riscv event standard. It has a non-
> standard
> events encoding for perf events and unimplemented MARCH and MIMP CSR.
> This patch add these events to support C9xx cpus.
> 
> AFAIK, at least the following chips used C9xx cpu.
> 
> * Allwinner D1 (C906)
> * T-HEAD th1520 (C910)
> * Sophgo mango (C920)
> 
> Inochi Amaoto (2):
>   perf tools riscv: Allow get_cpuid return empty MARCH and MIMP
>   perf vendor events riscv: add T-HEAD C9xx JSON file
> 
>  tools/perf/arch/riscv/util/header.c           |  7 +-
>  tools/perf/pmu-events/arch/riscv/mapfile.csv  |  1 +
>  .../arch/riscv/t-head/c9xx/cache.json         | 67
> ++++++++++++++++++
>  .../arch/riscv/t-head/c9xx/firmware.json      | 68
> +++++++++++++++++++
>  .../arch/riscv/t-head/c9xx/instruction.json   | 22 ++++++
>  .../arch/riscv/t-head/c9xx/microarch.json     | 42 ++++++++++++
>  6 files changed, 201 insertions(+), 6 deletions(-)
>  create mode 100644 tools/perf/pmu-events/arch/riscv/t-
> head/c9xx/cache.json
>  create mode 100644 tools/perf/pmu-events/arch/riscv/t-
> head/c9xx/firmware.json
>  create mode 100644 tools/perf/pmu-events/arch/riscv/t-
> head/c9xx/instruction.json
>  create mode 100644 tools/perf/pmu-events/arch/riscv/t-
> head/c9xx/microarch.json
> 
> --
> 2.40.1
> 
> 
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> linux-riscv mailing list
> linux-riscv@lists.infradead.org
> http://lists.infradead.org/mailman/listinfo/linux-riscv