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Mon, 9 Oct 2023 11:25:15 +0000 Received: from IA1PR20MB4953.namprd20.prod.outlook.com ([fe80::d050:882f:a8a7:8263]) by IA1PR20MB4953.namprd20.prod.outlook.com ([fe80::d050:882f:a8a7:8263%5]) with mapi id 15.20.6838.040; Mon, 9 Oct 2023 11:25:15 +0000 From: Inochi Amaoto <inochiama@outlook.com> To: Thomas Gleixner <tglx@linutronix.de>, Marc Zyngier <maz@kernel.org>, Rob Herring <robh+dt@kernel.org>, Krzysztof Kozlowski <krzysztof.kozlowski+dt@linaro.org>, Conor Dooley <conor+dt@kernel.org>, Palmer Dabbelt <palmer@dabbelt.com>, Paul Walmsley <paul.walmsley@sifive.com>, Chao Wei <chao.wei@sophgo.com>, Chen Wang <unicorn_wang@outlook.com>, Albert Ou <aou@eecs.berkeley.edu>, Daniel Lezcano <daniel.lezcano@linaro.org>, Anup Patel <anup@brainfault.org> Cc: Jisheng Zhang <jszhang@kernel.org>, Inochi Amaoto <inochiama@outlook.com>, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, linux-riscv@lists.infradead.org Subject: [PATCH v2 0/7] Add Huashan Pi board support Date: Mon, 9 Oct 2023 19:25:14 +0800 Message-ID: <IA1PR20MB49531C1C34C3E972DBBA4151BBCEA@IA1PR20MB4953.namprd20.prod.outlook.com> X-Mailer: git-send-email 2.42.0 Content-Transfer-Encoding: 8bit Content-Type: text/plain X-TMN: [8OJtKQ58U+IXxkwbUg2cUqt4spXaCenyyGuySXKtNhs=] X-ClientProxiedBy: SJ0PR13CA0153.namprd13.prod.outlook.com (2603:10b6:a03:2c7::8) To IA1PR20MB4953.namprd20.prod.outlook.com (2603:10b6:208:3af::19) X-Microsoft-Original-Message-ID: <20231009112517.477055-1-inochiama@outlook.com> MIME-Version: 1.0 X-MS-Exchange-MessageSentRepresentingType: 1 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: IA1PR20MB4953:EE_|PH0PR20MB6129:EE_ X-MS-Office365-Filtering-Correlation-Id: 5c499fb9-9a13-4916-28b4-08dbc8ba6865 X-Microsoft-Antispam: BCL:0; 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Add Huashan Pi board support
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Message
Inochi Amaoto
Oct. 9, 2023, 11:25 a.m. UTC
Huashan Pi board is an embedded development platform based on the CV1812H chip. Add minimal device tree files for this board. Currently, it can boot to a basic shell. NOTE: this series is based on the Jisheng's Milk-V Duo patch. Link: https://en.sophgo.com/product/introduce/huashan.html Link: https://en.sophgo.com/product/introduce/cv181xH.html Changed from v1: 1. split the patch into several patch and refactor them. Inochi Amaoto (7): dt-bindings: interrupt-controller: Add SOPHGO CV1812H plic dt-bindings: timer: Add SOPHGO CV1812H clint dt-bindings: riscv: Add SOPHGO Huashan Pi board compatibles riscv: dts: sophgo: Separate common devices from cv1800b soc riscv: dts: sophgo: cv180x: Add gpio devices riscv: dts: sophgo: add initial CV1812H SoC device tree riscv: dts: sophgo: add Huashan Pi board device tree .../sifive,plic-1.0.0.yaml | 1 + .../devicetree/bindings/riscv/sophgo.yaml | 4 + .../bindings/timer/sifive,clint.yaml | 1 + arch/riscv/boot/dts/sophgo/Makefile | 1 + arch/riscv/boot/dts/sophgo/cv1800b.dtsi | 95 +------------------ .../dts/sophgo/{cv1800b.dtsi => cv180x.dtsi} | 91 ++++++++++++++---- .../boot/dts/sophgo/cv1812h-huashan-pi.dts | 48 ++++++++++ arch/riscv/boot/dts/sophgo/cv1812h.dtsi | 36 +++++++ 8 files changed, 165 insertions(+), 112 deletions(-) copy arch/riscv/boot/dts/sophgo/{cv1800b.dtsi => cv180x.dtsi} (58%) create mode 100644 arch/riscv/boot/dts/sophgo/cv1812h-huashan-pi.dts create mode 100644 arch/riscv/boot/dts/sophgo/cv1812h.dtsi -- 2.42.0
Comments
On 09/10/2023 13:26, Inochi Amaoto wrote: > Add compatible string for SOPHGO CV1812H plic. > > Signed-off-by: Inochi Amaoto <inochiama@outlook.com> > --- > .../bindings/interrupt-controller/sifive,plic-1.0.0.yaml | 1 + > 1 file changed, 1 insertion(+) Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> --- This is an automated instruction, just in case, because many review tags are being ignored. If you know the process, you can skip it (please do not feel offended by me posting it here - no bad intentions intended). If you do not know the process, here is a short explanation: Please add Acked-by/Reviewed-by/Tested-by tags when posting new versions, under or above your Signed-off-by tag. Tag is "received", when provided in a message replied to you on the mailing list. Tools like b4 can help here. However, there's no need to repost patches *only* to add the tags. The upstream maintainer will do that for tags received on the version they apply. https://elixir.bootlin.com/linux/v6.5-rc3/source/Documentation/process/submitting-patches.rst#L577 Best regards, Krzysztof
On 2023/10/9 19:26, Inochi Amaoto wrote: > Add common GPIO devices for the CV180x and CV181x soc. > > Signed-off-by: Inochi Amaoto <inochiama@outlook.com> > --- > arch/riscv/boot/dts/sophgo/cv180x.dtsi | 72 ++++++++++++++++++++++++++ > 1 file changed, 72 insertions(+) > > diff --git a/arch/riscv/boot/dts/sophgo/cv180x.dtsi b/arch/riscv/boot/dts/sophgo/cv180x.dtsi > index ffaf51724c98..64ffb23d3626 100644 > --- a/arch/riscv/boot/dts/sophgo/cv180x.dtsi > +++ b/arch/riscv/boot/dts/sophgo/cv180x.dtsi > @@ -53,6 +53,78 @@ soc { > dma-noncoherent; > ranges; > > + gpio0: gpio@3020000 { > + compatible = "snps,dw-apb-gpio"; > + reg = <0x3020000 0x1000>; > + #address-cells = <1>; > + #size-cells = <0>; > + > + porta: gpio-controller@0 { > + compatible = "snps,dw-apb-gpio-port"; > + gpio-controller; > + #gpio-cells = <2>; > + ngpios = <32>; > + reg = <0>; > + interrupt-controller; > + #interrupt-cells = <2>; > + interrupts = <60 IRQ_TYPE_LEVEL_HIGH>; > + }; > + }; > + > + gpio1: gpio@3021000 { > + compatible = "snps,dw-apb-gpio"; > + reg = <0x3021000 0x1000>; > + #address-cells = <1>; > + #size-cells = <0>; > + > + portb: gpio-controller@0 { > + compatible = "snps,dw-apb-gpio-port"; > + gpio-controller; > + #gpio-cells = <2>; > + ngpios = <32>; > + reg = <0>; > + interrupt-controller; > + #interrupt-cells = <2>; > + interrupts = <61 IRQ_TYPE_LEVEL_HIGH>; > + }; > + }; > + > + gpio2: gpio@3022000 { > + compatible = "snps,dw-apb-gpio"; > + reg = <0x3022000 0x1000>; > + #address-cells = <1>; > + #size-cells = <0>; > + > + portc: gpio-controller@0 { > + compatible = "snps,dw-apb-gpio-port"; > + gpio-controller; > + #gpio-cells = <2>; > + ngpios = <32>; > + reg = <0>; > + interrupt-controller; > + #interrupt-cells = <2>; > + interrupts = <62 IRQ_TYPE_LEVEL_HIGH>; > + }; > + }; > + > + gpio3: gpio@3023000 { > + compatible = "snps,dw-apb-gpio"; > + reg = <0x3023000 0x1000>; > + #address-cells = <1>; > + #size-cells = <0>; > + > + portd: gpio-controller@0 { > + compatible = "snps,dw-apb-gpio-port"; > + gpio-controller; > + #gpio-cells = <2>; > + ngpios = <32>; > + reg = <0>; > + interrupt-controller; > + #interrupt-cells = <2>; > + interrupts = <63 IRQ_TYPE_LEVEL_HIGH>; > + }; > + }; > + > uart0: serial@4140000 { > compatible = "snps,dw-apb-uart"; > reg = <0x04140000 0x100>; LGTM Acked-by: Chen Wang <unicorn_wang@outlook.com> Thanks, Chen > -- > 2.42.0 >
On Mon, Oct 09, 2023 at 07:25:14PM +0800, Inochi Amaoto wrote: > Huashan Pi board is an embedded development platform based on the > CV1812H chip. Add minimal device tree files for this board. > Currently, it can boot to a basic shell. > > NOTE: this series is based on the Jisheng's Milk-V Duo patch. > > Link: https://en.sophgo.com/product/introduce/huashan.html > Link: https://en.sophgo.com/product/introduce/cv181xH.html > > Changed from v1: > 1. split the patch into several patch and refactor them. > > Inochi Amaoto (7): > dt-bindings: interrupt-controller: Add SOPHGO CV1812H plic > dt-bindings: timer: Add SOPHGO CV1812H clint > dt-bindings: riscv: Add SOPHGO Huashan Pi board compatibles > riscv: dts: sophgo: Separate common devices from cv1800b soc > riscv: dts: sophgo: cv180x: Add gpio devices > riscv: dts: sophgo: add initial CV1812H SoC device tree > riscv: dts: sophgo: add Huashan Pi board device tree For the patch series: Reviewed-by: Jisheng Zhang <jszhang@kernel.org> > > .../sifive,plic-1.0.0.yaml | 1 + > .../devicetree/bindings/riscv/sophgo.yaml | 4 + > .../bindings/timer/sifive,clint.yaml | 1 + > arch/riscv/boot/dts/sophgo/Makefile | 1 + > arch/riscv/boot/dts/sophgo/cv1800b.dtsi | 95 +------------------ > .../dts/sophgo/{cv1800b.dtsi => cv180x.dtsi} | 91 ++++++++++++++---- > .../boot/dts/sophgo/cv1812h-huashan-pi.dts | 48 ++++++++++ > arch/riscv/boot/dts/sophgo/cv1812h.dtsi | 36 +++++++ > 8 files changed, 165 insertions(+), 112 deletions(-) > copy arch/riscv/boot/dts/sophgo/{cv1800b.dtsi => cv180x.dtsi} (58%) > create mode 100644 arch/riscv/boot/dts/sophgo/cv1812h-huashan-pi.dts > create mode 100644 arch/riscv/boot/dts/sophgo/cv1812h.dtsi > > -- > 2.42.0 >
On 09/10/2023 13:25, Inochi Amaoto wrote: > Huashan Pi board is an embedded development platform based on the > CV1812H chip. Add minimal device tree files for this board. > Currently, it can boot to a basic shell. > > NOTE: this series is based on the Jisheng's Milk-V Duo patch. Which is? This must be clear dependency - lore link. Best regards, Krzysztof
On Fri, Oct 13, 2023 at 10:48:23AM +0200, Krzysztof Kozlowski wrote: > On 09/10/2023 13:25, Inochi Amaoto wrote: > > Huashan Pi board is an embedded development platform based on the > > CV1812H chip. Add minimal device tree files for this board. > > Currently, it can boot to a basic shell. > > > > NOTE: this series is based on the Jisheng's Milk-V Duo patch. > > Which is? This must be clear dependency - lore link. > https://lore.kernel.org/linux-riscv/20231006121449.721-1-jszhang@kernel.org/ AFAIK, This is merged in the for-next. > Best regards, > Krzysztof >
>On 09/10/2023 13:25, Inochi Amaoto wrote: >> Huashan Pi board is an embedded development platform based on the >> CV1812H chip. Add minimal device tree files for this board. >> Currently, it can boot to a basic shell. >> >> NOTE: this series is based on the Jisheng's Milk-V Duo patch. > >Which is? This must be clear dependency - lore link. > >Best regards, >Krzysztof https://lore.kernel.org/linux-riscv/c3920f4e-9e93-4a33-b3af-cc30cf6c1fe3@linaro.org/ AFAIK, this is already merged.