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Mon, 26 Feb 2024 05:50:33 +0000 From: Changhuang Liang To: Thomas Gleixner , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Philipp Zabel Cc: Ley Foon Tan , Jack Zhu , Changhuang Liang , linux-kernel@vger.kernel.org, devicetree@vger.kernel.org Subject: [PATCH v4 0/2] Add JH8100 external interrupt controller support Date: Sun, 25 Feb 2024 21:50:23 -0800 Message-Id: <20240226055025.1669223-1-changhuang.liang@starfivetech.com> X-Mailer: git-send-email 2.25.1 X-ClientProxiedBy: SH0PR01CA0006.CHNPR01.prod.partner.outlook.cn (2406:e500:c311:5::18) To SHXPR01MB0671.CHNPR01.prod.partner.outlook.cn (2406:e500:c311:25::10) Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: SHXPR01MB0671:EE_ X-MS-Office365-Filtering-Correlation-Id: 48ef64b8-860e-46b6-be76-08dc368ed8c9 X-MS-Exchange-SenderADCheck: 1 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: VqyhRCosvruoweP3zFvRPg9TAGDGNEo6VOQcqjR+aDI13Uhqe37vhjv0zyswP5Q6z4YnZ2xiyQuTGpbDtlX+eEK4FcaKIhIM/nVSxt3yZwMsfyMm10VCNfA8b+/m1bbyMKBduzhI5K7Zjd4mxjlTVr7I8i5EkPADiXa3wedD4ghkgvzUyRksFYsCxk6DymN8wq2MMhJRcaD86SQYG9nvDTgcdPi2HwgQW3uT+gwW9IhrdZIxScublFjLlwsGujM7cmRLGXDIir6rC+rrvIEg20ShIW0OtW9OMA6zNB3xAu9zz4bjJbxmb5v9I48qHG3mlNXbpEODBBlpcvThUzEWVf+7JzYWBtnb8CITaCF0+/vOJXwLmmit8sK9lv0LQ5jSAephhmL5L1nYiRq+IUC98PdLwSuRmXvziHoemJQLZzcje4aHTx8YbVygrLjUST8goman75V75Kwe8nxd0TvdVA5SbnDqBOJMSabtiZxExGYJLxEK37Pa5IQAKFozgbp/ZngVg7/o3LdSPui3WXJGqalMZahbZ48d1uu9lpvsv+jVfUvps2tQc2j/6CniMt52U4I2TQMJxe2CdI4tFb/sG6z7dbKOsJe9BV39E5DTL3Xh1RfMJE1mnOXZSZo0Z8e5 X-Forefront-Antispam-Report: CIP:255.255.255.255;CTRY:;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:SHXPR01MB0671.CHNPR01.prod.partner.outlook.cn;PTR:;CAT:NONE;SFS:(13230031)(230273577357003)(38350700005);DIR:OUT;SFP:1102; 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It can be used to handle high-level input interrupt signals. It also send the output interrupt signal to RISC-V PLIC. changes since v3: - Replaced "raw_spin_lock_irqsave" with "raw_spin_lock" - Replaced "raw_spin_unlock_irqsave" with "raw_spin_unlock" - Replaced "clear_bit" with "__clear_bit" v3: https://lore.kernel.org/all/20240221022647.5297-1-changhuang.liang@starfivetech.com/ changes since v2: - Rebased on tag v6.8-rc4. - Added raw_spinlock_t - Added irq_domain_remove free domain - Updated struct declarations and initializers - Updated variable declarations - Dropped store clk in struct starfive_irq_chip - Replaced "starfive_intc_mod" with "starfive_intc_bit_set&starfive_intc_bit_clear" - Replaced "struct irq_domain *root_domain" with "struct irq_domain *domain" - Added reset_control_assert&clk_disable_unprepare helper functions to error recover v2: https://lore.kernel.org/all/20240130055843.216342-1-changhuang.liang@starfivetech.com/ changes since v1: - Rebased on tag v6.8-rc1. - Dropped store reset_contorl. - Replaced "of_reset_control_get_by_index" with of_reset_control_get_exclusive - Printed the error code via %pe v1: https://lore.kernel.org/all/20240111023201.6187-1-changhuang.liang@starfivetech.com/ Changhuang Liang (2): dt-bindings: interrupt-controller: Add starfive,jh8100-intc irqchip: Add StarFive external interrupt controller .../starfive,jh8100-intc.yaml | 61 ++++++ MAINTAINERS | 6 + drivers/irqchip/Kconfig | 11 + drivers/irqchip/Makefile | 1 + drivers/irqchip/irq-starfive-jh8100-intc.c | 207 ++++++++++++++++++ 5 files changed, 286 insertions(+) create mode 100644 Documentation/devicetree/bindings/interrupt-controller/starfive,jh8100-intc.yaml create mode 100644 drivers/irqchip/irq-starfive-jh8100-intc.c --- 2.25.1