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b=H4sIAPV33GUC/2XMQQ7CIBCF4as0sxYzDqRJXXkP0wUUKJMoGDCoa bi72K3L/+Xl26C4zK7Aedggu8qFU+whDwMsQcfVCba9gZAU0mkU9iWCvWsxKmsXnLyRaKC/H9l 5fu/Sde4duDxT/uxwpd/6b1QSKIwiSROi9Epebhx1TseUV5hba1/oduAdnwAAAA== To: Jingoo Han , Gustavo Pimentel , Lorenzo Pieralisi , =?utf-8?q?Krzysztof_Wilczy=C5=84?= =?utf-8?q?ski?= , Rob Herring , Bjorn Helgaas , Marek Vasut , Yoshihiro Shimoda , Kishon Vijay Abraham I Cc: Serge Semin , linux-pci@vger.kernel.org, linux-kernel@vger.kernel.org, linux-renesas-soc@vger.kernel.org, linux-arm-msm@vger.kernel.org, mhi@lists.linux.dev, Manivannan Sadhasivam , Siddharth Vadapalli , Mrinmay Sarkar X-Mailer: b4 0.12.4 X-Developer-Signature: v=1; a=openpgp-sha256; l=2608; i=manivannan.sadhasivam@linaro.org; h=from:subject:message-id; bh=zN4H7AL9yEWwBMPFUse2kPeWuj9c3TyK31dCtLQBVwU=; b=owEBbQGS/pANAwAKAVWfEeb+kc71AcsmYgBl3Hf+ugscH906dxKa1q956AiK7dO/M8tdcr6fT aiph35AMmeJATMEAAEKAB0WIQRnpUMqgUjL2KRYJ5dVnxHm/pHO9QUCZdx3/gAKCRBVnxHm/pHO 9VIPB/90Qib9s9ybHOJjZTFAzC+LuAX4iTj/eAvrr+mXEaxKJgMyz/Zaxr3LoPGnq9TeHvyOSh+ rk8EqkZ8yGo+jFjQru/9eO3BCZEAaZQgbP4dgHuLgkKBkUOl91uC1af3moCy9egzAqAnXVcZJ2k lgcJf7eOuH+Db/euhh8+4bvApFvNG2KBCWI+e3lP8A4MARip6kPe7hc924+LzcG1RAg2CLJXK6w qGIQeCoU/d5wx0OiCOz8HGQpUWTXeTSDOes8m4P9WVTwWHQih8n5oYyZ8DV4yoURYsgxiaE43QX O+qByCZy8Q9LEQTmuuv+cv8fJuWCq5nxdUXlYbYny/O34vIw X-Developer-Key: i=manivannan.sadhasivam@linaro.org; a=openpgp; fpr=C668AEC3C3188E4C611465E7488550E901166008 X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1791961396832392974 X-GMAIL-MSGID: 1791961396832392974 Hello, This series adds support for integrating HDMA with the DWC EP driver. Hyper DMA (HDMA) is already supported by the dw-edma dmaengine driver. Unlike it's predecessor Embedded DMA (eDMA), HDMA supports only unroll mapping format and doesn't support auto detecting the read/write channels. Hence, this series modifies the existing eDMA code to work with HDMA by honoring the platform supplied mapping format and read/write channels count. The platform drivers making use of HDMA should pass the EDMA_MF_HDMA_NATIVE flag and provide channels count. In this series, HDMA support is added for the Qcom SA8775P SoC and the DMA support in enabled in MHI EPF driver as well. Testing ------- Tested on Qualcomm SA8775P Ride board. Dependency ---------- Depends on: https://lore.kernel.org/dmaengine/20240129-b4-feature_hdma_mainline-v7-0-8e8c1acb7a46@bootlin.com/ https://lore.kernel.org/all/1701432377-16899-1-git-send-email-quic_msarkar@quicinc.com/ NOTE: I've taken over this series from Mrinmay who posted v1: https://lore.kernel.org/linux-pci/1705669223-5655-1-git-send-email-quic_msarkar@quicinc.com/ - Mani Changes in v3: - Collected review tags - Minor code refactoring (Siddharth) - Link to v2: https://lore.kernel.org/r/20240216-dw-hdma-v2-0-b42329003f43@linaro.org Changes in v2: - Dropped dmaengine patches (Sergey) - Reworked dw_pcie_edma_find_chip() to support both eDMA and HDMA (Sergey) - Skipped MF and channel detection if glue drivers have provided them (Sergey) - Addressed review comments in pcie-qcom-ep and pci-epf-mhi drivers (Mani) Signed-off-by: Manivannan Sadhasivam Reviewed-by: Siddharth Vadapalli --- Manivannan Sadhasivam (3): PCI: dwc: Refactor dw_pcie_edma_find_chip() API PCI: dwc: Skip finding eDMA channels count if glue drivers have passed them PCI: dwc: Pass the eDMA mapping format flag directly from glue drivers Mrinmay Sarkar (2): PCI: qcom-ep: Add HDMA support for SA8775P SoC PCI: epf-mhi: Enable HDMA for SA8775P SoC drivers/pci/controller/dwc/pcie-designware.c | 74 +++++++++++++++++++--------- drivers/pci/controller/dwc/pcie-designware.h | 5 +- drivers/pci/controller/dwc/pcie-qcom-ep.c | 23 ++++++++- drivers/pci/controller/dwc/pcie-rcar-gen4.c | 2 +- drivers/pci/endpoint/functions/pci-epf-mhi.c | 1 + 5 files changed, 78 insertions(+), 27 deletions(-) --- base-commit: fdd10aee7740a53c370a867b8743a8c8945d1db1 change-id: 20240216-dw-hdma-64ddc09fb30b Best regards,