Message ID | 20240219140202.85680-1-christophe.kerello@foss.st.com |
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Mon, 19 Feb 2024 15:03:09 +0100 (CET) Received: from localhost (10.201.21.177) by SHFDAG1NODE3.st.com (10.75.129.71) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.27; Mon, 19 Feb 2024 15:03:09 +0100 From: Christophe Kerello <christophe.kerello@foss.st.com> To: <krzysztof.kozlowski@linaro.org>, <robh+dt@kernel.org>, <krzysztof.kozlowski+dt@linaro.org>, <conor+dt@kernel.org> CC: <linux-kernel@vger.kernel.org>, <linux-stm32@st-md-mailman.stormreply.com>, <devicetree@vger.kernel.org>, Christophe Kerello <christophe.kerello@foss.st.com> Subject: [PATCH v2 0/5] memory: stm32-fmc2-ebi: Add MP25 FMC2 support Date: Mon, 19 Feb 2024 15:01:57 +0100 Message-ID: <20240219140202.85680-1-christophe.kerello@foss.st.com> X-Mailer: git-send-email 2.25.1 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: <linux-kernel.vger.kernel.org> List-Subscribe: <mailto:linux-kernel+subscribe@vger.kernel.org> List-Unsubscribe: <mailto:linux-kernel+unsubscribe@vger.kernel.org> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Content-Type: text/plain X-ClientProxiedBy: EQNCAS1NODE3.st.com (10.75.129.80) To SHFDAG1NODE3.st.com (10.75.129.71) X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.272,Aquarius:18.0.1011,Hydra:6.0.619,FMLib:17.11.176.26 definitions=2024-02-19_09,2024-02-19_01,2023-05-22_02 X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1791336327021728160 X-GMAIL-MSGID: 1791336327021728160 |
Series |
memory: stm32-fmc2-ebi: Add MP25 FMC2 support
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Message
Christophe Kerello
Feb. 19, 2024, 2:01 p.m. UTC
On MP1 SoC, RNB signal (NAND controller signal) and NWAIT signal (PSRAM controller signal) have been integrated together in the SoC. That means that the NAND controller and the PSRAM controller (if the signal is used) can not be used at the same time. On MP25 SoC, the 2 signals can be used outside the SoC, so there is no more restrictions. MP1 SoC also embeds revision 1.1 of the FMC2 IP when MP25 SoC embeds revision 2.0 of the FMC2 IP. Changes in v2: - V1 patch 1 and 2 have been squashed and commit message has been updated. - V1 patch 3, 4 and 5 have been squashed and reworked. - V1 patch 7 has been renamed and associated commit message has been updated. - V1 patchset is split, one for memory, and another one for NAND. - Regmap_read API return value is checked everywhere it is called. - A platform data structure is handling the difference between MP1 and MP25. Christophe Kerello (5): dt-bindings: memory-controller: st,stm32: add MP25 support memory: stm32-fmc2-ebi: check regmap_read return value memory: stm32-fmc2-ebi: add MP25 support memory: stm32-fmc2-ebi: add MP25 RIF support memory: stm32-fmc2-ebi: keep power domain on .../memory-controllers/st,stm32-fmc2-ebi.yaml | 7 +- drivers/memory/stm32-fmc2-ebi.c | 739 ++++++++++++++++-- 2 files changed, 696 insertions(+), 50 deletions(-)