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AJvYcCUFAmydzdHVopXU4+m0b8XfQM2MXNPODWzTlia3hWv3P0ncABT2ywoOkaLQsi1UwBLWMMuijUd4IGiPFBXWR9WLzus8rKJplTRLmm3V X-Gm-Message-State: AOJu0Yw81+8wE1LwQA5N4VDlEX8M1u2IfaplQWUyg2RYNkBASkNIzwk2 cWfOoYk6wvSkyrzxVTiXKrk/DJP3gdEwCOSw4lo5RhN5IQnpdiKR3qLhb+IshTgmG98tm/aWPRT tFDKiJNFevD88Kmxiag== X-Received: from ericchancf.c.googlers.com ([fda3:e722:ac3:cc00:4f:4b78:c0a8:4139]) (user=ericchancf job=sendgmr) by 2002:a81:6c88:0:b0:607:8358:1a3d with SMTP id h130-20020a816c88000000b0060783581a3dmr1158404ywc.6.1708175534909; Sat, 17 Feb 2024 05:12:14 -0800 (PST) Date: Sat, 17 Feb 2024 13:12:06 +0000 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: Mime-Version: 1.0 X-Mailer: git-send-email 2.44.0.rc0.258.g7320e95886-goog Message-ID: <20240217131206.3667544-1-ericchancf@google.com> Subject: [PATCH v6 0/4] riscv/barrier: tidying up barrier-related macro From: Eric Chan To: paul.walmsley@sifive.com, palmer@dabbelt.com, aou@eecs.berkeley.edu Cc: linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org, ericchancf@google.com, conor.dooley@microchip.com, parri.andrea@gmail.com, emil.renner.berthing@canonical.com, samuel.holland@sifive.com X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1791151886501536796 X-GMAIL-MSGID: 1791151886501536796 This series makes barrier-related macro more neat and clear. This is a follow-up to [0-3], change to multiple patches, for readability, create new message thread. v5 -> v6: [PATCH 1/4] let this change to pass review by checkpatch.pl instead of overwriting again in [PATCH 4/4]. for [PATCH 4/4] change the error message example in commit message to make it more relevant v4 -> v5: [PATCH 3/4] __atomic_acquire_fence and __atomic_release_fence omit-the-fence-on-uniprocessor optimization, and fix the typo of RISCV_RELEASE_BARRIER when spliting the patch in v3. v3 -> v4: fix [PATCH 1/4] commit message weird line breaks and let [PATCH 3/4] fix the form that can pass the checking of checkpatch.pl. v2 -> v3: split the patch into multiple patches for one problem per patch. Also review the changelog to make the description more precise. v1 -> v2: makes compilation pass with allyesconfig instead of defconfig only, also satisfy scripts/checkpatch.pl. - (__asm__ __volatile__ (RISCV_FENCE_ASM(p, s) : : : "memory")) + ({ __asm__ __volatile__ (RISCV_FENCE_ASM(p, s) : : : "memory"); }) [0](v1/v2) https://lore.kernel.org/lkml/20240209125048.4078639-1-ericchancf@google.com/ [1] (v3) https://lore.kernel.org/lkml/20240213142856.2416073-1-ericchancf@google.com/ [2] (v4) https://lore.kernel.org/lkml/20240213200923.2547570-1-ericchancf@google.com/ [4] (v5) https://lore.kernel.org/lkml/20240213223810.2595804-1-ericchancf@google.com/ Eric Chan (4): riscv/barrier: Define __{mb,rmb,wmb} riscv/barrier: Define RISCV_FULL_BARRIER riscv/barrier: Consolidate fence definitions riscv/barrier: Resolve checkpatch.pl error arch/riscv/include/asm/atomic.h | 17 ++++++++--------- arch/riscv/include/asm/barrier.h | 21 ++++++++++----------- arch/riscv/include/asm/cmpxchg.h | 5 ++--- arch/riscv/include/asm/fence.h | 10 ++++++++-- arch/riscv/include/asm/io.h | 8 ++++---- arch/riscv/include/asm/mmio.h | 5 +++-- arch/riscv/include/asm/mmiowb.h | 2 +- 7 files changed, 36 insertions(+), 32 deletions(-) Reviewed-by: Andrea Parri --- 2.44.0.rc0.258.g7320e95886-goog