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AJvYcCV+JNDIEqIo4wyyZ1wqvmIxjpERpksYhD6CfxU4UEqn7EK3I2l8ms76p1SH3Uj3XjO96kjqQpqexHPXiKcJIH33mhMuxBCKFyxnP7Um X-Gm-Message-State: AOJu0YxlFhYN/QRjUfJP1DDFPiCfs6o5J1Hi3r23vzFuz5t4onDqIRTE n0yjXMzNpPTuzSpme/rGyUkRsMb2PNB3niFIHWERPQTsOdvupWs5cCBeWlzKJz3hdQiaTfgwG6I qDouM3ttm1Bf494e7Ng== X-Received: from ericchancf.c.googlers.com ([fda3:e722:ac3:cc00:4f:4b78:c0a8:4139]) (user=ericchancf job=sendgmr) by 2002:a05:6902:1007:b0:dc9:5ef8:2b2d with SMTP id w7-20020a056902100700b00dc95ef82b2dmr175464ybt.4.1707863897101; Tue, 13 Feb 2024 14:38:17 -0800 (PST) Date: Tue, 13 Feb 2024 22:38:09 +0000 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: Mime-Version: 1.0 X-Mailer: git-send-email 2.43.0.687.g38aa6559b0-goog Message-ID: <20240213223810.2595804-1-ericchancf@google.com> Subject: [PATCH v5 0/4] riscv/barrier: tidying up barrier-related macro From: Eric Chan To: paul.walmsley@sifive.com, palmer@dabbelt.com, aou@eecs.berkeley.edu Cc: linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org, ericchancf@google.com X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1790794184096524557 X-GMAIL-MSGID: 1790825515934805350 This series makes barrier-related macro more neat and clear. This is a follow-up to [0-2], change to multiple patches, for readability, create new message thread. v4 -> v5: [PATCH 3/4] __atomic_acquire_fence and __atomic_release_fence omit-the-fence-on-uniprocessor optimization, and fix the typo of RISCV_RELEASE_BARRIER when spliting the patch in v3. v3 -> v4: fix [PATCH 1/4] commit message weird line breaks and let [PATCH 3/4] fix the form that can pass the checking of checkpatch.pl. v2 -> v3: split the patch into multiple patches for one problem per patch. Also review the changelog to make the description more precise. v1 -> v2: makes compilation pass with allyesconfig instead of defconfig only, also satisfy scripts/checkpatch.pl. - (__asm__ __volatile__ (RISCV_FENCE_ASM(p, s) : : : "memory")) + ({ __asm__ __volatile__ (RISCV_FENCE_ASM(p, s) : : : "memory"); }) [0](v1/v2) https://lore.kernel.org/lkml/20240209125048.4078639-1-ericchancf@google.com/ [1] (v3) https://lore.kernel.org/lkml/20240213142856.2416073-1-ericchancf@google.com/ [2] (v4) https://lore.kernel.org/lkml/20240213200923.2547570-1-ericchancf@google.com/ Eric Chan (4): riscv/barrier: Define __{mb,rmb,wmb} riscv/barrier: Define RISCV_FULL_BARRIER riscv/barrier: Consolidate fence definitions riscv/barrier: Resolve checkpatch.pl error arch/riscv/include/asm/atomic.h | 17 ++++++++--------- arch/riscv/include/asm/barrier.h | 21 ++++++++++----------- arch/riscv/include/asm/cmpxchg.h | 5 ++--- arch/riscv/include/asm/fence.h | 10 ++++++++-- arch/riscv/include/asm/io.h | 8 ++++---- arch/riscv/include/asm/mmio.h | 5 +++-- arch/riscv/include/asm/mmiowb.h | 2 +- 7 files changed, 36 insertions(+), 32 deletions(-) --- 2.43.0.687.g38aa6559b0-goog