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Mon, 12 Feb 2024 15:36:30 -0800 (PST) From: Charlie Jenkins Subject: [PATCH v11 0/4] riscv: Create and document PR_RISCV_SET_ICACHE_FLUSH_CTX prctl Date: Mon, 12 Feb 2024 15:36:25 -0800 Message-Id: <20240212-fencei-v11-0-e1327f25fe10@rivosinc.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-B4-Tracking: v=1; b=H4sIAHmrymUC/23SS07EMAwG4KuMsqbIdpxHWXEPxKJ5MVnQjlpUg UZzd9IR00Yoy1j5fjtWrmKJc46LeDldxRzXvORpLAfEp5Pw52H8iF0OpSAISCKi6VIcfcxd6pO GYCynAUS5fJljyt/3pLf3cj7n5Wuaf+7BK27VvwiiR8SKHXQuerCI3hHS65zXacmjf/bTp9hSV qqkhF1SkeSdJjk4dJgaUh6SUO5Sbj2NQmVJ2uhMQ/JDMiDsD165yMA+UXI9qCAbUtXS7lIVOQw YFQZDRK1pdS37XeoigRF1sczKN6SpJB67NUUam0AjRwwOGtLWUu/SFsly4LI1TkDYkH0l6dhtv /XEMq5L0QbTkgg15eMrwLYjUr3BxBIw/LO32+0XwJEEjKwCAAA= To: Paul Walmsley , Palmer Dabbelt , Albert Ou , Jonathan Corbet , Conor Dooley , =?utf-8?b?Q2zDqW1lbnQgTMOpZ2Vy?= , Atish Patra , Randy Dunlap , Alexandre Ghiti Cc: linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org, linux-doc@vger.kernel.org, Charlie Jenkins , Atish Patra , Alexandre Ghiti X-Mailer: b4 0.12.3 X-Developer-Signature: v=1; a=ed25519-sha256; t=1707780989; l=3458; i=charlie@rivosinc.com; s=20231120; h=from:subject:message-id; bh=pUkJcJN2rctCyQ0hK/qiJS411FCsdKiJii0pjIPLWbg=; b=MPwj9l2ctTE9U5PMrkcabg29HVx1LnyHJJ9FmdT2NRt6a6jiZmF+27/ABOvnKjANPSgri2Nzk yny/fD+G20bBSrkLd6AMgL81mkbhViWypSaZGxhLbhPl1JRHJHuVKKM X-Developer-Key: i=charlie@rivosinc.com; a=ed25519; pk=t4RSWpMV1q5lf/NWIeR9z58bcje60/dbtxxmoSfBEcs= X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1790738197188807238 X-GMAIL-MSGID: 1790738197188807238 Improve the performance of icache flushing by creating a new prctl flag PR_RISCV_SET_ICACHE_FLUSH_CTX. The interface is left generic to allow for future expansions such as with the proposed J extension [1]. Documentation is also provided to explain the use case. Patch sent to add PR_RISCV_SET_ICACHE_FLUSH_CTX to man-pages [2]. [1] https://github.com/riscv/riscv-j-extension [2] https://lore.kernel.org/linux-man/20240124-fencei_prctl-v1-1-0bddafcef331@rivosinc.com Signed-off-by: Charlie Jenkins --- Changes in v11: - Add back PR_RISCV_CTX_SW_FENCEI_OFF (Samuel) - Fix under nosmp (Samuel) - Change set_prev_cpu (Samuel) - Fixup example testcase in docs - Change wording of documentation slightly (Alejandor Colomar) - Link to v10: https://lore.kernel.org/r/20240124-fencei-v10-0-a25971f4301d@rivosinc.com Changes in v10: - Fix fence.i condition to properly only flush on migration (Alex) - Fix documentation wording (Alex) - Link to v9: https://lore.kernel.org/r/20240123-fencei-v9-0-71411bfe8d71@rivosinc.com Changes in v9: - Remove prev_cpu from mm (Alex) - Link to v8: https://lore.kernel.org/r/20240116-fencei-v8-0-43a42134f021@rivosinc.com Changes in v8: - Only flush icache if migrated to different cpu (Alex) - Move flushing to switch_to to catch per-thread flushing properly - Link to v7: https://lore.kernel.org/r/20240112-fencei-v7-0-78f0614e1db0@rivosinc.com Changes in v7: - Change "per_thread" parameter to "scope" and provide constants for the parameter. - Link to v6: https://lore.kernel.org/r/20240109-fencei-v6-0-04116e51445c@rivosinc.com Changes in v6: - Fixup documentation formatting - Link to v5: https://lore.kernel.org/r/20240108-fencei-v5-0-aa1e51d7222f@rivosinc.com Changes in v5: - Minor documentation changes (Randy) - Link to v4: https://lore.kernel.org/r/20240107-fencei-v4-0-d4cf2fb905d3@rivosinc.com Changes in v4: - Add OFF flag to disallow fence.i in userspace (Atish) - Fix documentation issues (Atish) - Link to v3: https://lore.kernel.org/r/20231213-fencei-v3-0-b75158238eb7@rivosinc.com Changes in v3: - Check if value force_icache_flush set on thread, rather than in mm twice (Clément) - Link to v2: https://lore.kernel.org/r/20231130-fencei-v2-0-2cb623ab1b1f@rivosinc.com Changes in v2: - Fix kernel-doc comment (Conor) - Link to v1: https://lore.kernel.org/r/20231122-fencei-v1-0-bec0811cb212@rivosinc.com --- Charlie Jenkins (4): riscv: Remove unnecessary irqflags processor.h include riscv: Include riscv_set_icache_flush_ctx prctl documentation: Document PR_RISCV_SET_ICACHE_FLUSH_CTX prctl cpumask: Add assign cpu Documentation/arch/riscv/cmodx.rst | 98 ++++++++++++++++++++++++++++++++++ Documentation/arch/riscv/index.rst | 1 + arch/riscv/include/asm/irqflags.h | 1 - arch/riscv/include/asm/mmu.h | 2 + arch/riscv/include/asm/processor.h | 12 +++++ arch/riscv/include/asm/switch_to.h | 23 ++++++++ arch/riscv/mm/cacheflush.c | 105 +++++++++++++++++++++++++++++++++++++ arch/riscv/mm/context.c | 18 +++++-- include/linux/cpumask.h | 16 ++++++ include/uapi/linux/prctl.h | 6 +++ kernel/sys.c | 6 +++ 11 files changed, 282 insertions(+), 6 deletions(-) --- base-commit: 6613476e225e090cc9aad49be7fa504e290dd33d change-id: 20231117-fencei-f9f60d784fa0