[v7,0/4] kvm: arm64: allow the VM to select DEVICE_* and NORMAL_NC for IO memory

  From: Ankit Agrawal <ankita@nvidia.com>

Currently, KVM for ARM64 maps at stage 2 memory that is considered device
with DEVICE_nGnRE memory attributes; this setting overrides (per
ARM architecture [1]) any device MMIO mapping present at stage 1,
resulting in a set-up whereby a guest operating system cannot
determine device MMIO mapping memory attributes on its own but
it is always overridden by the KVM stage 2 default.

This set-up does not allow guest operating systems to select device
memory attributes independently from KVM stage-2 mappings
(refer to [1], "Combining stage 1 and stage 2 memory type attributes"),
which turns out to be an issue in that guest operating systems
(e.g. Linux) may request to map devices MMIO regions with memory
attributes that guarantee better performance (e.g. gathering
attribute - that for some devices can generate larger PCIe memory
writes TLPs) and specific operations (e.g. unaligned transactions)
such as the NormalNC memory type.

The default device stage 2 mapping was chosen in KVM for ARM64 since
it was considered safer (i.e. it would not allow guests to trigger
uncontained failures ultimately crashing the machine) but this
turned out to be asynchronous (SError) defeating the purpose.

For these reasons, relax the KVM stage 2 device memory attributes
from DEVICE_nGnRE to Normal-NC.

Generalizing to other devices may be problematic, however. E.g.
GICv2 VCPU interface, which is effectively a shared peripheral, can
allow a guest to affect another guest's interrupt distribution. Hence
limit the change to VFIO PCI as caution. This is achieved by
making the VFIO PCI core module set a flag that is tested by KVM
to activate the code. This could be extended to other devices in
the future once that is deemed safe.

[1] section D8.5 - DDI0487J_a_a-profile_architecture_reference_manual.pdf

Applied over v6.8-rc2.

History
=======
v6 -> v7
- Changed VM_VFIO_ALLOW_WC to VM_ALLOW_ANY_UNCACHED based on suggestion
  from Alex Williamson.
- Refactored stage2_set_prot_attr() based on Will's suggestion to
  reorganize the switch cases. Also updated the case to return -EINVAL
  when both KVM_PGTABLE_PROT_DEVICE and KVM_PGTABLE_PROT_NORMAL_NC set.
- Fixed nits pointed by Oliver and Catalin.

v5 -> v6
- Rebased to v6.8-rc2

v4 -> v5
- Moved the cover letter description text to patch 1/4.
- Cleaned up stage2_set_prot_attr() based on Marc Zyngier suggestions.
- Moved the mm header file changes to a separate patch.
- Rebased to v6.7-rc3.

v3 -> v4
- Moved the vfio-pci change to use the VM_VFIO_ALLOW_WC into
  separate patch.
- Added check to warn on the case NORMAL_NC and DEVICE are
  set simultaneously.
- Fixed miscellaneous nitpicks suggested in v3.

v2 -> v3
- Added a new patch (and converted to patch series) suggested by
  Catalin Marinas to ensure the code changes are restricted to
  VFIO PCI devices.
- Introduced VM_VFIO_ALLOW_WC flag for VFIO PCI to communicate
  with VMM.
- Reverted GIC mapping to DEVICE.

v1 -> v2
- Updated commit log to the one posted by
  Lorenzo Pieralisi <lpieralisi@kernel.org> (Thanks!)
- Added new flag to represent the NORMAL_NC setting. Updated
  stage2_set_prot_attr() to handle new flag.

v6 Link:
https://lore.kernel.org/all/20240207204652.22954-1-ankita@nvidia.com/

Suggested-by: Jason Gunthorpe <jgg@nvidia.com>
Acked-by: Catalin Marinas <catalin.marinas@arm.com>
Signed-off-by: Ankit Agrawal <ankita@nvidia.com>

Ankit Agrawal (4):
  kvm: arm64: introduce new flag for non-cacheable IO memory
  mm: introduce new flag to indicate wc safe
  kvm: arm64: set io memory s2 pte as normalnc for vfio pci device
  vfio: convey kvm that the vfio-pci device is wc safe

 arch/arm64/include/asm/kvm_pgtable.h |  2 ++
 arch/arm64/include/asm/memory.h      |  2 ++
 arch/arm64/kvm/hyp/pgtable.c         | 24 +++++++++++++++++++-----
 arch/arm64/kvm/mmu.c                 | 14 ++++++++++----
 drivers/vfio/pci/vfio_pci_core.c     |  6 +++++-
 include/linux/mm.h                   | 14 ++++++++++++++
 6 files changed, 52 insertions(+), 10 deletions(-)
  

On 11.02.24 18:47, ankita@nvidia.com wrote:
> From: Ankit Agrawal <ankita@nvidia.com>
> 

Hi,

> Currently, KVM for ARM64 maps at stage 2 memory that is considered device
> with DEVICE_nGnRE memory attributes; this setting overrides (per
> ARM architecture [1]) any device MMIO mapping present at stage 1,
> resulting in a set-up whereby a guest operating system cannot
> determine device MMIO mapping memory attributes on its own but
> it is always overridden by the KVM stage 2 default.
> 
> This set-up does not allow guest operating systems to select device
> memory attributes independently from KVM stage-2 mappings
> (refer to [1], "Combining stage 1 and stage 2 memory type attributes"),
> which turns out to be an issue in that guest operating systems
> (e.g. Linux) may request to map devices MMIO regions with memory
> attributes that guarantee better performance (e.g. gathering
> attribute - that for some devices can generate larger PCIe memory
> writes TLPs) and specific operations (e.g. unaligned transactions)
> such as the NormalNC memory type.
> 
> The default device stage 2 mapping was chosen in KVM for ARM64 since
> it was considered safer (i.e. it would not allow guests to trigger
> uncontained failures ultimately crashing the machine) but this
> turned out to be asynchronous (SError) defeating the purpose.
> 
> For these reasons, relax the KVM stage 2 device memory attributes
> from DEVICE_nGnRE to Normal-NC.
> 
> Generalizing to other devices may be problematic, however. E.g.
> GICv2 VCPU interface, which is effectively a shared peripheral, can
> allow a guest to affect another guest's interrupt distribution. Hence
> limit the change to VFIO PCI as caution. This is achieved by
> making the VFIO PCI core module set a flag that is tested by KVM
> to activate the code. This could be extended to other devices in
> the future once that is deemed safe.

I still have to digest some of the stuff I learned about this issue, 
please bear with me :)

(1) PCI BARs might contain mixtures of RAM and MMIO, the exact 
locations/semantics within a BAR are only really known to the actual 
device driver.

We must not unconditionally map PFNs "the wrong way", because it can 
have undesired side effects. Side effects might include 
read-speculation, that can be very problematic with MMIO regions.

The safe way (for the host) is DEVICE_nGnRE. But that is actually 
problematic for performance (where we want WC?) and unaligned accesses 
(where we want NC?).

We can trigger both cases right now inside VMs, where we want the device 
driver to actually make the decision.


(2) For a VM, that device driver lives inside the VM, for DPDK and 
friends, it lives in user space. They have this information.

We only focus here on optimizing (fixing?) the mapping for VMs, DPDK is 
out of the picture. So we want to allow the VM to achieve a WC/NC 
mapping by using a relaxed (NC) mapping in stage-1. Whatever is set in 
stage-2 wins.


(3) vfio knows whether using WC (and NC?) could be problematic, and must 
forbid it, if that is the case. There are cases where we could otherwise 
cause harm (bring down the host?). We must keep mapping the memory as 
DEVICE_nGnRE when in doubt.


Now, what the new mmap() flag does is tell the world "using the wrong 
mapping type cannot bring down the host", and KVM uses that to use a 
different mapping type (NC) in stage-1 as setup by vfio in the user 
space page tables.

I was trying to find ways of avoiding a mmap() flag and was hoping that 
we could just use a PTE bit that does not have semantics in VM_PFNMAP 
mappings. Unfortunately, arm64 does not support uffd-wp, which I had in 
mind, so it's not that easy.


Further, I was wondering if there would be a way to let DPDK similarly 
benefit, because it looks like we are happily ignoring that (I was told 
they apply some hacks to work around that).


In essence, user space knows how it will consume that memory: QEMU wants 
to mmap() it only to get it into stage-1 and not access it via the user 
page tables. DPDK wants to mmap() it to actually access it from user space.


So I am curious, is the following problematic, and why:

(a) User space tells VFIO which parts of a BAR it would like to have 
mapped differently. For QEMU, this would mean, requesting a NC mapping 
for the whole BAR. For DPDK, it could mean requesting different types 
for parts of a BAR.

(b) VFIO decides if it is safe to use a relaxed mapping. If in doubt, it 
falls back to existing (legacy) handling -- DEVICE_nGnRE.

(c) KVM simply uses the existing mapping type instead of diverging from 
the one in the user space mapping.


That would mean, that we would map NC already in QEMU. I wonder if that 
could be a problem with read speculation, even if QEMU never really 
accesses that mmap'ed region.

Something like that would of course require user space changes. Handling 
it without such changes (ignoring DPDK of course) would require some 
information exchange between KVM and vfio, like the mmap flag proposed.
  

On Mon, Feb 12, 2024 at 11:26:12AM +0100, David Hildenbrand wrote:

> I still have to digest some of the stuff I learned about this issue, please
> bear with me :)
> 
> (1) PCI BARs might contain mixtures of RAM and MMIO, the exact
> locations/semantics within a BAR are only really known to the actual device
> driver.

Nit: Not RAM and MMIO but different kinds of MMIO that have different
access patterns. The conclusion is correct.

> We must not unconditionally map PFNs "the wrong way", because it can have
> undesired side effects. Side effects might include read-speculation, that
> can be very problematic with MMIO regions.

It is worse that some hand wavey "side effect". If you map memory with
NORMAL_NC (ie for write combining) then writel() doesn't work
correctly at all.

The memory must be mapped according to which kernel APIs the actual
driver in the VM will use. writel() vs __iowrite64_copy().

> We can trigger both cases right now inside VMs, where we want the device
> driver to actually make the decision.

Yes
 
> (2) For a VM, that device driver lives inside the VM, for DPDK and friends,
> it lives in user space. They have this information.

Yes
 
> We only focus here on optimizing (fixing?) the mapping for VMs, DPDK is out
> of the picture.

DPDK will be solved through some VFIO ioctl, we know how to do it,
just nobody has cared enough to do it.

> So we want to allow the VM to achieve a WC/NC mapping by using a
> relaxed (NC) mapping in stage-1. Whatever is set in stage-2 wins.

Yes
 
> 
> (3) vfio knows whether using WC (and NC?) could be problematic, and must
> forbid it, if that is the case. There are cases where we could otherwise
> cause harm (bring down the host?). We must keep mapping the memory as
> DEVICE_nGnRE when in doubt.

Yes, there is an unspecific fear that on ARM platforms using NORMAL_NC
in the wrong way can trigger a catastrophic error and kill the
host. There is no way to know if the platform has this bug, so the
agreement was to be conservative and only allow it for vfio-pci, based
on some specific details of how PCI has to be implemented and ARM
guidance on PCI integration..

> Now, what the new mmap() flag does is tell the world "using the wrong
> mapping type cannot bring down the host", and KVM uses that to use a
> different mapping type (NC) in stage-1 as setup by vfio in the user space
> page tables.

The inverse meaning, we assume VMAs with the flag can bring down the
host, but yes.

> I was trying to find ways of avoiding a mmap() flag and was hoping that we
> could just use a PTE bit that does not have semantics in VM_PFNMAP mappings.
> Unfortunately, arm64 does not support uffd-wp, which I had in mind, so it's
> not that easy.

Seems like a waste of a valuable PTE bit to me.

> Further, I was wondering if there would be a way to let DPDK similarly
> benefit, because it looks like we are happily ignoring that (I was told they
> apply some hacks to work around that).

dpdk doesn't need the VMA bit, we know how to solve it with vfio
ioctls, it is very straightforward. dpdk just does a ioctl & mmap and
VFIO will create a vma with pgprote_writecombine(). Completely
trivial, the only nasty bit is fitting this into the VFIO uAPI.

> (a) User space tells VFIO which parts of a BAR it would like to have mapped
> differently. For QEMU, this would mean, requesting a NC mapping for the
> whole BAR. For DPDK, it could mean requesting different types for parts of a
> BAR.

We don't want to have have the memory mapped as NC in qemu. As I said
above if it is mapped NC then writel() doesn't work. We can't have
conflicting mappings that go toward NC when the right answer is
DEVICE. 

writel() on NC will malfunction.

__iowrite64_copy() on DEVICE will be functionally correct but slower.

The S2 mapping that KVM creates is special because it doesn't actually
map it once the VM kernel gets started. The VM kernel always supplies
a S1 table that sets the correct type.

So if qemu has DEVICE, the S2 has NC and the VM's S1 has DEVICE then
the mapping is realiably made to be DEVICE. The hidden S2 doesn't
cause a problem.

> That would mean, that we would map NC already in QEMU. I wonder if that
> could be a problem with read speculation, even if QEMU never really accesses
> that mmap'ed region.

Also correct.

Further, qemu may need to do emulation for MMIO in various cases and
the qemu logic for this requires a DEVICE mapping or the emulation
will malfunction.

Using NC in qemu is off the table.

Jason
  

Hi Jason,

Thanks for all the details (some might be valuable to document in more 
detail, but I'm not that experienced with all of the mapping types on 
arm64, so it might "just be me").

> It is worse that some hand wavey "side effect". If you map memory with
> NORMAL_NC (ie for write combining) then writel() doesn't work
> correctly at all.
> 
> The memory must be mapped according to which kernel APIs the actual
> driver in the VM will use. writel() vs __iowrite64_copy().
> 
>> We can trigger both cases right now inside VMs, where we want the device
>> driver to actually make the decision.
> 
> Yes
>   
>> (2) For a VM, that device driver lives inside the VM, for DPDK and friends,
>> it lives in user space. They have this information.
> 
> Yes
>   
>> We only focus here on optimizing (fixing?) the mapping for VMs, DPDK is out
>> of the picture.
> 
> DPDK will be solved through some VFIO ioctl, we know how to do it,
> just nobody has cared enough to do it.

Good!

> 
>> So we want to allow the VM to achieve a WC/NC mapping by using a
>> relaxed (NC) mapping in stage-1. Whatever is set in stage-2 wins.
> 
> Yes
>   
>>
>> (3) vfio knows whether using WC (and NC?) could be problematic, and must
>> forbid it, if that is the case. There are cases where we could otherwise
>> cause harm (bring down the host?). We must keep mapping the memory as
>> DEVICE_nGnRE when in doubt.
> 
> Yes, there is an unspecific fear that on ARM platforms using NORMAL_NC
> in the wrong way can trigger a catastrophic error and kill the
> host. There is no way to know if the platform has this bug, so the
> agreement was to be conservative and only allow it for vfio-pci, based
> on some specific details of how PCI has to be implemented and ARM
> guidance on PCI integration..
> 
>> Now, what the new mmap() flag does is tell the world "using the wrong
>> mapping type cannot bring down the host", and KVM uses that to use a
>> different mapping type (NC) in stage-1 as setup by vfio in the user space
>> page tables.
> 
> The inverse meaning, we assume VMAs with the flag can bring down the
> host, but yes.

Got it, will have a closer look at the patch soon.

> 
>> I was trying to find ways of avoiding a mmap() flag and was hoping that we
>> could just use a PTE bit that does not have semantics in VM_PFNMAP mappings.
>> Unfortunately, arm64 does not support uffd-wp, which I had in mind, so it's
>> not that easy.
> 
> Seems like a waste of a valuable PTE bit to me.

It would rather have been "it's already unused there, so let's reuse 
it". But there was no such low-hanging gruit.

> 
>> Further, I was wondering if there would be a way to let DPDK similarly
>> benefit, because it looks like we are happily ignoring that (I was told they
>> apply some hacks to work around that).
> 
> dpdk doesn't need the VMA bit, we know how to solve it with vfio
> ioctls, it is very straightforward. dpdk just does a ioctl & mmap and
> VFIO will create a vma with pgprote_writecombine(). Completely
> trivial, the only nasty bit is fitting this into the VFIO uAPI.

That's what I thought.

> 
>> (a) User space tells VFIO which parts of a BAR it would like to have mapped
>> differently. For QEMU, this would mean, requesting a NC mapping for the
>> whole BAR. For DPDK, it could mean requesting different types for parts of a
>> BAR.
> 
> We don't want to have have the memory mapped as NC in qemu. As I said
> above if it is mapped NC then writel() doesn't work. We can't have
> conflicting mappings that go toward NC when the right answer is
> DEVICE.

I was wondering who would trigger that, but as I read below it could be 
MMIO emulation.

> 
> writel() on NC will malfunction.
> 
> __iowrite64_copy() on DEVICE will be functionally correct but slower.
> 
> The S2 mapping that KVM creates is special because it doesn't actually
> map it once the VM kernel gets started. The VM kernel always supplies
> a S1 table that sets the correct type.
> 
> So if qemu has DEVICE, the S2 has NC and the VM's S1 has DEVICE then
> the mapping is realiably made to be DEVICE. The hidden S2 doesn't
> cause a problem.
> 
>> That would mean, that we would map NC already in QEMU. I wonder if that
>> could be a problem with read speculation, even if QEMU never really accesses
>> that mmap'ed region.
> 
> Also correct.
> 
> Further, qemu may need to do emulation for MMIO in various cases and
> the qemu logic for this requires a DEVICE mapping or the emulation
> will malfunction.
> 
> Using NC in qemu is off the table.

Good, thanks for the details, all makes sense to me.
  

On Sun, Feb 11, 2024 at 11:17:01PM +0530, ankita@nvidia.com wrote:
> From: Ankit Agrawal <ankita@nvidia.com>
> 
> Currently, KVM for ARM64 maps at stage 2 memory that is considered device
> with DEVICE_nGnRE memory attributes; this setting overrides (per
> ARM architecture [1]) any device MMIO mapping present at stage 1,
> resulting in a set-up whereby a guest operating system cannot
> determine device MMIO mapping memory attributes on its own but
> it is always overridden by the KVM stage 2 default.
> 
> This set-up does not allow guest operating systems to select device
> memory attributes independently from KVM stage-2 mappings
> (refer to [1], "Combining stage 1 and stage 2 memory type attributes"),
> which turns out to be an issue in that guest operating systems
> (e.g. Linux) may request to map devices MMIO regions with memory
> attributes that guarantee better performance (e.g. gathering
> attribute - that for some devices can generate larger PCIe memory
> writes TLPs) and specific operations (e.g. unaligned transactions)
> such as the NormalNC memory type.
> 
> The default device stage 2 mapping was chosen in KVM for ARM64 since
> it was considered safer (i.e. it would not allow guests to trigger
> uncontained failures ultimately crashing the machine) but this
> turned out to be asynchronous (SError) defeating the purpose.
> 
> For these reasons, relax the KVM stage 2 device memory attributes
> from DEVICE_nGnRE to Normal-NC.

Hi Ankit,

Thanks for being responsive in respinning the series according to the
feedback. I think we're pretty close here, but it'd be good to address
the comment / changelog feedback as well.

Can you respin this once more? Hopefully we can get this stuff soaking
in -next thereafter.
  

>>
>> The default device stage 2 mapping was chosen in KVM for ARM64 since
>> it was considered safer (i.e. it would not allow guests to trigger
>> uncontained failures ultimately crashing the machine) but this
>> turned out to be asynchronous (SError) defeating the purpose.
>>
>> For these reasons, relax the KVM stage 2 device memory attributes
>> from DEVICE_nGnRE to Normal-NC.
>
> Hi Ankit,
>
> Thanks for being responsive in respinning the series according to the
> feedback. I think we're pretty close here, but it'd be good to address
> the comment / changelog feedback as well.
>
> Can you respin this once more? Hopefully we can get this stuff soaking
> in -next thereafter.

Hi Oliver, yes I am planning to refresh it in the next few days after
incorporating the comments.