[00/17] clk: renesas: rzg2l: Add support for power domains

  From: Claudiu Beznea <claudiu.beznea.uj@bp.renesas.com>

Hi,

Series adds support for power domains on rzg2l driver.

RZ/G2L kind of devices support a functionality called MSTOP (module
stop/standby). According to hardware manual the module could be switch
to standby after its clocks are disabled. The reverse order of operation
should be done when enabling a module (get the module out of standby,
enable its clocks etc).

In [1] the MSTOP settings were implemented by adding code in driver
to attach the MSTOP state to the IP clocks. But it has been proposed
to implement it as power domain. The result is this series.

Along with MSTOP functionality there is also module power down
functionality (which is currently available only on RZ/G3S). This has
been also implemented through power domains.

The DT bindings were updated with power domain IDs (plain integers
that matches the DT with driver data structures). The current DT
bindings were updated with module IDs for the modules listed in tables
with name "Registers for Module Standby Mode" (see HW manual) exception
being RZ/G3S where, due to the power down functionality, the DDR,
TZCDDR, OTFDE_DDR were also added, to avoid system being blocked due
to the following lines of code from patch 7/17.

+       /* Prepare for power down the BUSes in power down mode. */
+       if (info->pm_domain_pwrdn_mstop)
+               writel(CPG_PWRDN_MSTOP_ENABLE, priv->base + CPG_PWRDN_MSTOP);

Domain IDs were added to all SoC specific bindings to avoid breaking
dt schema validation failures.

If the proposed dt-binding update is good for you, please let me know
if you want me to also update the individual dt schemas to reflect
the newly introduced power domain IDs in schema examples, if any.

Thank you,
Claudiu Beznea 

[1] https://lore.kernel.org/all/20231120070024.4079344-4-claudiu.beznea.uj@bp.renesas.com/

Claudiu Beznea (17):
  dt-bindings: clock: r9a07g043-cpg: Add power domain IDs
  dt-bindings: clock: r9a07g044-cpg: Add power domain IDs
  dt-bindings: clock: r9a07g054-cpg: Add power domain IDs
  dt-bindings: clock: r9a08g045-cpg: Add power domain IDs
  dt-bindings: clock: r9a09g011-cpg: Add always-on power domain IDs
  dt-bindings: clock: renesas,rzg2l-cpg: Update #power-domain-cells =
    <1>
  clk: renesas: rzg2l: Extend power domain support
  clk: renesas: r9a07g043: Add initial support for power domains
  clk: renesas: r9a07g044: Add initial support for power domains
  clk: renesas: r9a08g045: Add support for power domains
  clk: renesas: r9a09g011: Add initial support for power domains
  arm64: dts: renesas: rzg3s-smarc-som: Guard the ethernet IRQ GPIOs
    with proper flags
  arm64: dts: renesas: r9a07g043: Update #power-domain-cells = <1>
  arm64: dts: renesas: r9a07g044: Update #power-domain-cells = <1>
  arm64: dts: renesas: r9a07g054: Update #power-domain-cells = <1>
  arm64: dts: renesas: r9a08g045: Update #power-domain-cells = <1>
  arm64: dts: renesas: r9a09g011: Update #power-domain-cells = <1>

 .../bindings/clock/renesas,rzg2l-cpg.yaml     |   4 +-
 arch/arm64/boot/dts/renesas/r9a07g043.dtsi    |  84 +++----
 arch/arm64/boot/dts/renesas/r9a07g043u.dtsi   |   6 +-
 arch/arm64/boot/dts/renesas/r9a07g044.dtsi    | 100 ++++----
 arch/arm64/boot/dts/renesas/r9a07g054.dtsi    | 100 ++++----
 arch/arm64/boot/dts/renesas/r9a08g045.dtsi    |  20 +-
 arch/arm64/boot/dts/renesas/r9a09g011.dtsi    |  28 +--
 .../boot/dts/renesas/rzg3s-smarc-som.dtsi     |   4 +
 arch/riscv/boot/dts/renesas/r9a07g043f.dtsi   |   2 +-
 drivers/clk/renesas/r9a07g043-cpg.c           |   9 +
 drivers/clk/renesas/r9a07g044-cpg.c           |  13 +
 drivers/clk/renesas/r9a08g045-cpg.c           |  27 +++
 drivers/clk/renesas/r9a09g011-cpg.c           |   9 +
 drivers/clk/renesas/rzg2l-cpg.c               | 227 ++++++++++++++++--
 drivers/clk/renesas/rzg2l-cpg.h               |  68 ++++++
 include/dt-bindings/clock/r9a07g043-cpg.h     |  48 ++++
 include/dt-bindings/clock/r9a07g044-cpg.h     |  58 +++++
 include/dt-bindings/clock/r9a07g054-cpg.h     |  58 +++++
 include/dt-bindings/clock/r9a08g045-cpg.h     |  70 ++++++
 include/dt-bindings/clock/r9a09g011-cpg.h     |   3 +
 20 files changed, 752 insertions(+), 186 deletions(-)
  

Hi Claudiu,

Thanks for the patch.

> -----Original Message-----
> From: Claudiu <claudiu.beznea@tuxon.dev>
> Sent: Thursday, February 8, 2024 12:43 PM
> Subject: [PATCH 01/17] dt-bindings: clock: r9a07g043-cpg: Add power domain
> IDs
> 
> From: Claudiu Beznea <claudiu.beznea.uj@bp.renesas.com>
> 
> Add power domain IDs for RZ/G2UL (R9A07G043) SoC.
> 
> Signed-off-by: Claudiu Beznea <claudiu.beznea.uj@bp.renesas.com>
> ---
>  include/dt-bindings/clock/r9a07g043-cpg.h | 48 +++++++++++++++++++++++
>  1 file changed, 48 insertions(+)
> 
> diff --git a/include/dt-bindings/clock/r9a07g043-cpg.h b/include/dt-
> bindings/clock/r9a07g043-cpg.h
> index 77cde8effdc7..eabfeec7ac37 100644
> --- a/include/dt-bindings/clock/r9a07g043-cpg.h
> +++ b/include/dt-bindings/clock/r9a07g043-cpg.h
> @@ -200,5 +200,53 @@
>  #define R9A07G043_AX45MP_CORE0_RESETN	78	/* RZ/Five Only */
>  #define R9A07G043_IAX45_RESETN		79	/* RZ/Five Only */
> 
> +/* Power domain IDs. */
> +#define R9A07G043_PD_ALWAYS_ON		0
> +#define R9A07G043_PD_GIC		1
> +#define R9A07G043_PD_IA55		2
> +#define R9A07G043_PD_MHU		3
> +#define R9A07G043_PD_CORESIGHT		4
> +#define R9A07G043_PD_SYC		5
> +#define R9A07G043_PD_DMAC		6
> +#define R9A07G043_PD_GTM0		7
> +#define R9A07G043_PD_GTM1		8
> +#define R9A07G043_PD_GTM2		9
> +#define R9A07G043_PD_MTU		10
> +#define R9A07G043_PD_POE3		11
> +#define R9A07G043_PD_WDT0		12
> +#define R9A07G043_PD_SPI		13
> +#define R9A07G043_PD_SDHI0		14
> +#define R9A07G043_PD_SDHI1		15
> +#define R9A07G043_PD_ISU		16
> +#define R9A07G043_PD_CRU		17
> +#define R9A07G043_PD_LCDC		18
> +#define R9A07G043_PD_SSI0		19
> +#define R9A07G043_PD_SSI1		20
> +#define R9A07G043_PD_SSI2		21
> +#define R9A07G043_PD_SSI3		22
> +#define R9A07G043_PD_SRC		23
> +#define R9A07G043_PD_USB0		24
> +#define R9A07G043_PD_USB1		25
> +#define R9A07G043_PD_USB_PHY		26
> +#define R9A07G043_PD_ETHER0		27
> +#define R9A07G043_PD_ETHER1		28
> +#define R9A07G043_PD_I2C0		29
> +#define R9A07G043_PD_I2C1		30
> +#define R9A07G043_PD_I2C2		31
> +#define R9A07G043_PD_I2C3		32
> +#define R9A07G043_PD_SCIF0		33
> +#define R9A07G043_PD_SCIF1		34
> +#define R9A07G043_PD_SCIF2		35
> +#define R9A07G043_PD_SCIF3		36
> +#define R9A07G043_PD_SCIF4		37
> +#define R9A07G043_PD_SCI0		38
> +#define R9A07G043_PD_SCI1		39
> +#define R9A07G043_PD_IRDA		40
> +#define R9A07G043_PD_RSPI0		41
> +#define R9A07G043_PD_RSPI1		42
> +#define R9A07G043_PD_RSPI2		43
> +#define R9A07G043_PD_CANFD		44
> +#define R9A07G043_PD_ADC		45
> +#define R9A07G043_PD_TSU		46

Not sure from "Table 42.3 Registers for Module Standby Mode"

Power domain ID has to be based on CPG_BUS_***_MSTOP or CPG_CLKON_***
As former reduces number of IDs??

Cheers,
Biju
  

Hi, Biju,

On 08.02.2024 16:30, Biju Das wrote:
> Hi Claudiu,
> 
> Thanks for the patch.
> 
>> -----Original Message-----
>> From: Claudiu <claudiu.beznea@tuxon.dev>
>> Sent: Thursday, February 8, 2024 12:43 PM
>> Subject: [PATCH 01/17] dt-bindings: clock: r9a07g043-cpg: Add power domain
>> IDs
>>
>> From: Claudiu Beznea <claudiu.beznea.uj@bp.renesas.com>
>>
>> Add power domain IDs for RZ/G2UL (R9A07G043) SoC.
>>
>> Signed-off-by: Claudiu Beznea <claudiu.beznea.uj@bp.renesas.com>
>> ---
>>  include/dt-bindings/clock/r9a07g043-cpg.h | 48 +++++++++++++++++++++++
>>  1 file changed, 48 insertions(+)
>>
>> diff --git a/include/dt-bindings/clock/r9a07g043-cpg.h b/include/dt-
>> bindings/clock/r9a07g043-cpg.h
>> index 77cde8effdc7..eabfeec7ac37 100644
>> --- a/include/dt-bindings/clock/r9a07g043-cpg.h
>> +++ b/include/dt-bindings/clock/r9a07g043-cpg.h
>> @@ -200,5 +200,53 @@
>>  #define R9A07G043_AX45MP_CORE0_RESETN	78	/* RZ/Five Only */
>>  #define R9A07G043_IAX45_RESETN		79	/* RZ/Five Only */
>>
>> +/* Power domain IDs. */
>> +#define R9A07G043_PD_ALWAYS_ON		0
>> +#define R9A07G043_PD_GIC		1
>> +#define R9A07G043_PD_IA55		2
>> +#define R9A07G043_PD_MHU		3
>> +#define R9A07G043_PD_CORESIGHT		4
>> +#define R9A07G043_PD_SYC		5
>> +#define R9A07G043_PD_DMAC		6
>> +#define R9A07G043_PD_GTM0		7
>> +#define R9A07G043_PD_GTM1		8
>> +#define R9A07G043_PD_GTM2		9
>> +#define R9A07G043_PD_MTU		10
>> +#define R9A07G043_PD_POE3		11
>> +#define R9A07G043_PD_WDT0		12
>> +#define R9A07G043_PD_SPI		13
>> +#define R9A07G043_PD_SDHI0		14
>> +#define R9A07G043_PD_SDHI1		15
>> +#define R9A07G043_PD_ISU		16
>> +#define R9A07G043_PD_CRU		17
>> +#define R9A07G043_PD_LCDC		18
>> +#define R9A07G043_PD_SSI0		19
>> +#define R9A07G043_PD_SSI1		20
>> +#define R9A07G043_PD_SSI2		21
>> +#define R9A07G043_PD_SSI3		22
>> +#define R9A07G043_PD_SRC		23
>> +#define R9A07G043_PD_USB0		24
>> +#define R9A07G043_PD_USB1		25
>> +#define R9A07G043_PD_USB_PHY		26
>> +#define R9A07G043_PD_ETHER0		27
>> +#define R9A07G043_PD_ETHER1		28
>> +#define R9A07G043_PD_I2C0		29
>> +#define R9A07G043_PD_I2C1		30
>> +#define R9A07G043_PD_I2C2		31
>> +#define R9A07G043_PD_I2C3		32
>> +#define R9A07G043_PD_SCIF0		33
>> +#define R9A07G043_PD_SCIF1		34
>> +#define R9A07G043_PD_SCIF2		35
>> +#define R9A07G043_PD_SCIF3		36
>> +#define R9A07G043_PD_SCIF4		37
>> +#define R9A07G043_PD_SCI0		38
>> +#define R9A07G043_PD_SCI1		39
>> +#define R9A07G043_PD_IRDA		40
>> +#define R9A07G043_PD_RSPI0		41
>> +#define R9A07G043_PD_RSPI1		42
>> +#define R9A07G043_PD_RSPI2		43
>> +#define R9A07G043_PD_CANFD		44
>> +#define R9A07G043_PD_ADC		45
>> +#define R9A07G043_PD_TSU		46
> 
> Not sure from "Table 42.3 Registers for Module Standby Mode"
> 
> Power domain ID has to be based on CPG_BUS_***_MSTOP or CPG_CLKON_***
> As former reduces number of IDs??

If I understand correctly your point here, you want me to describe PM
domain in DT with something like:

power-domains = <&cpg CPG_BUS_X_MSTOP>;

where X={ACPU, PERI_CPU, PERI_CPU2, REG0, REG1} ?

With this, I still see the necessity of a 3rd identifier that will be IP
specific to be able to uniquely match b/w DT description and registered
power domain. FMPOV, this will lead to a more complicated implementation.

We need a unique ID that the pm domain xlate will use to xlate the DT
binding to driver data structures.

Thank you,
Claudiu Beznea
> 
> Cheers,
> Biju
> 
>  
>
  

> -----Original Message-----
> From: claudiu beznea <claudiu.beznea@tuxon.dev>
> Sent: Thursday, February 8, 2024 3:46 PM
> Subject: Re: [PATCH 01/17] dt-bindings: clock: r9a07g043-cpg: Add power
> domain IDs
> 
> Hi, Biju,
> 
> On 08.02.2024 16:30, Biju Das wrote:
> > Hi Claudiu,
> >
> > Thanks for the patch.
> >
> >> -----Original Message-----
> >> From: Claudiu <claudiu.beznea@tuxon.dev>
> >> Sent: Thursday, February 8, 2024 12:43 PM
> >> Subject: [PATCH 01/17] dt-bindings: clock: r9a07g043-cpg: Add power
> >> domain IDs
> >>
> >> From: Claudiu Beznea <claudiu.beznea.uj@bp.renesas.com>
> >>
> >> Add power domain IDs for RZ/G2UL (R9A07G043) SoC.
> >>
> >> Signed-off-by: Claudiu Beznea <claudiu.beznea.uj@bp.renesas.com>
> >> ---
> >>  include/dt-bindings/clock/r9a07g043-cpg.h | 48
> >> +++++++++++++++++++++++
> >>  1 file changed, 48 insertions(+)
> >>
> >> diff --git a/include/dt-bindings/clock/r9a07g043-cpg.h b/include/dt-
> >> bindings/clock/r9a07g043-cpg.h index 77cde8effdc7..eabfeec7ac37
> >> 100644
> >> --- a/include/dt-bindings/clock/r9a07g043-cpg.h
> >> +++ b/include/dt-bindings/clock/r9a07g043-cpg.h
> >> @@ -200,5 +200,53 @@
> >>  #define R9A07G043_AX45MP_CORE0_RESETN	78	/* RZ/Five Only */
> >>  #define R9A07G043_IAX45_RESETN		79	/* RZ/Five Only */
> >>
> >> +/* Power domain IDs. */
> >> +#define R9A07G043_PD_ALWAYS_ON		0
> >> +#define R9A07G043_PD_GIC		1
> >> +#define R9A07G043_PD_IA55		2
> >> +#define R9A07G043_PD_MHU		3
> >> +#define R9A07G043_PD_CORESIGHT		4
> >> +#define R9A07G043_PD_SYC		5
> >> +#define R9A07G043_PD_DMAC		6
> >> +#define R9A07G043_PD_GTM0		7
> >> +#define R9A07G043_PD_GTM1		8
> >> +#define R9A07G043_PD_GTM2		9
> >> +#define R9A07G043_PD_MTU		10
> >> +#define R9A07G043_PD_POE3		11
> >> +#define R9A07G043_PD_WDT0		12
> >> +#define R9A07G043_PD_SPI		13
> >> +#define R9A07G043_PD_SDHI0		14
> >> +#define R9A07G043_PD_SDHI1		15
> >> +#define R9A07G043_PD_ISU		16
> >> +#define R9A07G043_PD_CRU		17
> >> +#define R9A07G043_PD_LCDC		18
> >> +#define R9A07G043_PD_SSI0		19
> >> +#define R9A07G043_PD_SSI1		20
> >> +#define R9A07G043_PD_SSI2		21
> >> +#define R9A07G043_PD_SSI3		22
> >> +#define R9A07G043_PD_SRC		23
> >> +#define R9A07G043_PD_USB0		24
> >> +#define R9A07G043_PD_USB1		25
> >> +#define R9A07G043_PD_USB_PHY		26
> >> +#define R9A07G043_PD_ETHER0		27
> >> +#define R9A07G043_PD_ETHER1		28
> >> +#define R9A07G043_PD_I2C0		29
> >> +#define R9A07G043_PD_I2C1		30
> >> +#define R9A07G043_PD_I2C2		31
> >> +#define R9A07G043_PD_I2C3		32
> >> +#define R9A07G043_PD_SCIF0		33
> >> +#define R9A07G043_PD_SCIF1		34
> >> +#define R9A07G043_PD_SCIF2		35
> >> +#define R9A07G043_PD_SCIF3		36
> >> +#define R9A07G043_PD_SCIF4		37
> >> +#define R9A07G043_PD_SCI0		38
> >> +#define R9A07G043_PD_SCI1		39
> >> +#define R9A07G043_PD_IRDA		40
> >> +#define R9A07G043_PD_RSPI0		41
> >> +#define R9A07G043_PD_RSPI1		42
> >> +#define R9A07G043_PD_RSPI2		43
> >> +#define R9A07G043_PD_CANFD		44
> >> +#define R9A07G043_PD_ADC		45
> >> +#define R9A07G043_PD_TSU		46
> >
> > Not sure from "Table 42.3 Registers for Module Standby Mode"
> >
> > Power domain ID has to be based on CPG_BUS_***_MSTOP or CPG_CLKON_***
> > As former reduces number of IDs??
> 
> If I understand correctly your point here, you want me to describe PM
> domain in DT with something like:
> 
> power-domains = <&cpg CPG_BUS_X_MSTOP>;

MSTOP bits are distinct for each IP.

<&cpg CPG_BUS_MCPU1_MSTOP x>; x =1..9

2=MTU IP

4= GPT

etc...

Is it something work??

> 
> where X={ACPU, PERI_CPU, PERI_CPU2, REG0, REG1} ?
> 
> With this, I still see the necessity of a 3rd identifier that will be IP
> specific to be able to uniquely match b/w DT description and registered
> power domain. FMPOV, this will lead to a more complicated implementation.
> 
> We need a unique ID that the pm domain xlate will use to xlate the DT
> binding to driver data structures.

Ok.

Cheers,
Biju
  

> -----Original Message-----
> From: claudiu beznea <claudiu.beznea@tuxon.dev>
> Sent: Thursday, February 8, 2024 4:53 PM
> To: Biju Das <biju.das.jz@bp.renesas.com>; geert+renesas@glider.be;
> mturquette@baylibre.com; sboyd@kernel.org; robh@kernel.org;
> krzysztof.kozlowski+dt@linaro.org; conor+dt@kernel.org;
> magnus.damm@gmail.com; paul.walmsley@sifive.com; palmer@dabbelt.com;
> aou@eecs.berkeley.edu
> Cc: linux-renesas-soc@vger.kernel.org; linux-clk@vger.kernel.org;
> devicetree@vger.kernel.org; linux-kernel@vger.kernel.org; linux-
> riscv@lists.infradead.org; Claudiu Beznea
> <claudiu.beznea.uj@bp.renesas.com>
> Subject: Re: [PATCH 01/17] dt-bindings: clock: r9a07g043-cpg: Add power
> domain IDs
> 
> 
> 
> On 08.02.2024 18:28, Biju Das wrote:
> >
> >
> >> -----Original Message-----
> >> From: claudiu beznea <claudiu.beznea@tuxon.dev>
> >> Sent: Thursday, February 8, 2024 3:46 PM
> >> Subject: Re: [PATCH 01/17] dt-bindings: clock: r9a07g043-cpg: Add
> >> power domain IDs
> >>
> >> Hi, Biju,
> >>
> >> On 08.02.2024 16:30, Biju Das wrote:
> >>> Hi Claudiu,
> >>>
> >>> Thanks for the patch.
> >>>
> >>>> -----Original Message-----
> >>>> From: Claudiu <claudiu.beznea@tuxon.dev>
> >>>> Sent: Thursday, February 8, 2024 12:43 PM
> >>>> Subject: [PATCH 01/17] dt-bindings: clock: r9a07g043-cpg: Add power
> >>>> domain IDs
> >>>>
> >>>> From: Claudiu Beznea <claudiu.beznea.uj@bp.renesas.com>
> >>>>
> >>>> Add power domain IDs for RZ/G2UL (R9A07G043) SoC.
> >>>>
> >>>> Signed-off-by: Claudiu Beznea <claudiu.beznea.uj@bp.renesas.com>
> >>>> ---
> >>>>  include/dt-bindings/clock/r9a07g043-cpg.h | 48
> >>>> +++++++++++++++++++++++
> >>>>  1 file changed, 48 insertions(+)
> >>>>
> >>>> diff --git a/include/dt-bindings/clock/r9a07g043-cpg.h
> >>>> b/include/dt- bindings/clock/r9a07g043-cpg.h index
> >>>> 77cde8effdc7..eabfeec7ac37
> >>>> 100644
> >>>> --- a/include/dt-bindings/clock/r9a07g043-cpg.h
> >>>> +++ b/include/dt-bindings/clock/r9a07g043-cpg.h
> >>>> @@ -200,5 +200,53 @@
> >>>>  #define R9A07G043_AX45MP_CORE0_RESETN	78	/* RZ/Five Only */
> >>>>  #define R9A07G043_IAX45_RESETN		79	/* RZ/Five Only */
> >>>>
> >>>> +/* Power domain IDs. */
> >>>> +#define R9A07G043_PD_ALWAYS_ON		0
> >>>> +#define R9A07G043_PD_GIC		1
> >>>> +#define R9A07G043_PD_IA55		2
> >>>> +#define R9A07G043_PD_MHU		3
> >>>> +#define R9A07G043_PD_CORESIGHT		4
> >>>> +#define R9A07G043_PD_SYC		5
> >>>> +#define R9A07G043_PD_DMAC		6
> >>>> +#define R9A07G043_PD_GTM0		7
> >>>> +#define R9A07G043_PD_GTM1		8
> >>>> +#define R9A07G043_PD_GTM2		9
> >>>> +#define R9A07G043_PD_MTU		10
> >>>> +#define R9A07G043_PD_POE3		11
> >>>> +#define R9A07G043_PD_WDT0		12
> >>>> +#define R9A07G043_PD_SPI		13
> >>>> +#define R9A07G043_PD_SDHI0		14
> >>>> +#define R9A07G043_PD_SDHI1		15
> >>>> +#define R9A07G043_PD_ISU		16
> >>>> +#define R9A07G043_PD_CRU		17
> >>>> +#define R9A07G043_PD_LCDC		18
> >>>> +#define R9A07G043_PD_SSI0		19
> >>>> +#define R9A07G043_PD_SSI1		20
> >>>> +#define R9A07G043_PD_SSI2		21
> >>>> +#define R9A07G043_PD_SSI3		22
> >>>> +#define R9A07G043_PD_SRC		23
> >>>> +#define R9A07G043_PD_USB0		24
> >>>> +#define R9A07G043_PD_USB1		25
> >>>> +#define R9A07G043_PD_USB_PHY		26
> >>>> +#define R9A07G043_PD_ETHER0		27
> >>>> +#define R9A07G043_PD_ETHER1		28
> >>>> +#define R9A07G043_PD_I2C0		29
> >>>> +#define R9A07G043_PD_I2C1		30
> >>>> +#define R9A07G043_PD_I2C2		31
> >>>> +#define R9A07G043_PD_I2C3		32
> >>>> +#define R9A07G043_PD_SCIF0		33
> >>>> +#define R9A07G043_PD_SCIF1		34
> >>>> +#define R9A07G043_PD_SCIF2		35
> >>>> +#define R9A07G043_PD_SCIF3		36
> >>>> +#define R9A07G043_PD_SCIF4		37
> >>>> +#define R9A07G043_PD_SCI0		38
> >>>> +#define R9A07G043_PD_SCI1		39
> >>>> +#define R9A07G043_PD_IRDA		40
> >>>> +#define R9A07G043_PD_RSPI0		41
> >>>> +#define R9A07G043_PD_RSPI1		42
> >>>> +#define R9A07G043_PD_RSPI2		43
> >>>> +#define R9A07G043_PD_CANFD		44
> >>>> +#define R9A07G043_PD_ADC		45
> >>>> +#define R9A07G043_PD_TSU		46
> >>>
> >>> Not sure from "Table 42.3 Registers for Module Standby Mode"
> >>>
> >>> Power domain ID has to be based on CPG_BUS_***_MSTOP or
> >>> CPG_CLKON_*** As former reduces number of IDs??
> >>
> >> If I understand correctly your point here, you want me to describe PM
> >> domain in DT with something like:
> >>
> >> power-domains = <&cpg CPG_BUS_X_MSTOP>;
> >
> > MSTOP bits are distinct for each IP.
> >
> > <&cpg CPG_BUS_MCPU1_MSTOP x>; x =1..9
> >
> > 2=MTU IP
> >
> > 4= GPT
> >
> > etc...
> >
> > Is it something work??
> 
> It might work. But:
> 
> - you have to consider that some IPs have more than one MSTOP bit, thus,
> do
>   we want to uniquely identify these with all MSTOP bits (thus the 2nd
> cell
>   being a bitmask) or only one is enough?

We can have an encoding in that case 8:16 24 bit entries

> - some HW blocks (e.g. OTFDE_DDR) have no MSTOP bits associated (as of my
>   current research), so, only PWRDN

Why do we want to add power domain support for DDR?

> - some HW blocks have both MSTOP and PWRDN

That will be an array right?

> - if future hardware implementation will spread the MSTOP bits for one IP
>   to more than one register then this proposal will not work

That will be an array right?

Cheers,
Biju
  

On 08/02/2024 13:42, Claudiu wrote:
> From: Claudiu Beznea <claudiu.beznea.uj@bp.renesas.com>
> 
> The driver will be modified (in the next commits) to be able to specify
> individual power domain ID for each IP. Update the documentation to cope
> with this.

You are affecting existing users, so you should explain that you keep
ABI intact or if you break it, why it is fine to do so.



Best regards,
Krzysztof
  

On 09.02.2024 09:56, Krzysztof Kozlowski wrote:
> On 08/02/2024 13:42, Claudiu wrote:
>> From: Claudiu Beznea <claudiu.beznea.uj@bp.renesas.com>
>>
>> The driver will be modified (in the next commits) to be able to specify
>> individual power domain ID for each IP. Update the documentation to cope
>> with this.
> 
> You are affecting existing users, so you should explain that you keep
> ABI intact or if you break it, why it is fine to do so.
> 

OK, I'll improve the description. The ABI will not be broken with the
changes in this series.

Thank you,
Claudiu Beznea

> 
> 
> Best regards,
> Krzysztof
>