Message ID | 20240207225526.3953230-1-jm@ti.com |
---|---|
Headers |
Return-Path: <linux-kernel+bounces-57278-ouuuleilei=gmail.com@vger.kernel.org> Delivered-To: ouuuleilei@gmail.com Received: by 2002:a05:7301:168b:b0:106:860b:bbdd with SMTP id ma11csp2552827dyb; Wed, 7 Feb 2024 14:57:06 -0800 (PST) X-Google-Smtp-Source: AGHT+IH4w5HkNbFWLPcA0JK33jMgzrFzBYSW0C6MUSLHFcGmP24+vZ0KwM/GZfphSg+uy62UlETN X-Received: by 2002:aa7:8745:0:b0:6e0:7308:7325 with SMTP id g5-20020aa78745000000b006e073087325mr714233pfo.1.1707346626335; Wed, 07 Feb 2024 14:57:06 -0800 (PST) ARC-Seal: i=2; a=rsa-sha256; t=1707346626; cv=pass; d=google.com; s=arc-20160816; b=lF43o9OTH+AHuZ2F7SBzqe30EK4pKUiSi9+RVUJYvjXWYgL1mF8aHBpV9BcXDQ4EzM WWONuN4C+JAw9z4aYV/NU2G9NjvuFhQIzExN8XxZNuhVZ6+Uc/AH3Uk8q8rLtmlx/IoH N9qeAelzhY0TyKU5BQJiOHiOBjoaPHYyQlIO7h5RXJL6hRHRYts7Uo8zOVbPXlgRWOhv yO03cbUpKszN03vn7mL4oXlMZikz5asIvrSrZ4DHR04ySOp+GUHybbLzqZynfnwQgn1y BZh2jwsaL4azsKR+n+vz7rV7yiaVw5TWoobemFO58JkFHkXrzupuz53Q9kYu6Gp19wWz KXsQ== ARC-Message-Signature: i=2; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=content-transfer-encoding:mime-version:list-unsubscribe :list-subscribe:list-id:precedence:message-id:date:subject:cc:to :from:dkim-signature; bh=zOoJZOLG26Ul8soZA3DhrVj70l4+Sl0iEM4P7gItmx8=; fh=iKB9KRI3+Dm0Qk48cFrgIy4+sFNemtHcDIi1HrvDG8A=; b=H2ETwQvhcmh+xQWUT39Gok6hkDBzrEiVNKhq9/1Q9SIDh6U4L6ipIVsJIS8jzJBzXe qGcD0NQPcPAwjB5z26TTcWXHu2Lbt2zEM5nhe5rd9vY6o6Tu4c8C+eE9gF3nt21K0OiT bGRYW8G8e7Uqbqor6uhkMxvE62E5M3UgMwP1SLK1Hf4EsI9ch7GqJm1PV41v7/8/fOqT zcwOWXimnIee0vO9ncHVEQiq6web/sTYk0ui1jkxaBhTm+/DjElXbuo6tWZ/hPOijTUb 2jC43RYyGwylI9bARFObvb3mJTFiHyXTc0ue/Fo3X/0zWsNDDOXL9dyw/uJWaEBDtK1F 8W/g==; dara=google.com ARC-Authentication-Results: i=2; mx.google.com; dkim=pass header.i=@ti.com header.s=ti-com-17Q1 header.b="DLyh20/s"; arc=pass (i=1 spf=pass spfdomain=ti.com dkim=pass dkdomain=ti.com dmarc=pass fromdomain=ti.com); spf=pass (google.com: domain of linux-kernel+bounces-57278-ouuuleilei=gmail.com@vger.kernel.org designates 2604:1380:40f1:3f00::1 as permitted sender) smtp.mailfrom="linux-kernel+bounces-57278-ouuuleilei=gmail.com@vger.kernel.org"; dmarc=pass (p=QUARANTINE sp=NONE dis=NONE) header.from=ti.com X-Forwarded-Encrypted: i=2; AJvYcCVCCjf+NfqseDwgSQ0toWvuunJyQvjkhN3zhjAz+BWxTC9lMgD0vEhASm/ot7Zp1UIGtJdlZ3yOfQNCs0HQVI3oYSQwng== Received: from sy.mirrors.kernel.org (sy.mirrors.kernel.org. [2604:1380:40f1:3f00::1]) by mx.google.com with ESMTPS id q5-20020a656a85000000b005d6dd7fab87si2634181pgu.884.2024.02.07.14.57.05 for <ouuuleilei@gmail.com> (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 07 Feb 2024 14:57:06 -0800 (PST) Received-SPF: pass (google.com: domain of linux-kernel+bounces-57278-ouuuleilei=gmail.com@vger.kernel.org designates 2604:1380:40f1:3f00::1 as permitted sender) client-ip=2604:1380:40f1:3f00::1; Authentication-Results: mx.google.com; dkim=pass header.i=@ti.com header.s=ti-com-17Q1 header.b="DLyh20/s"; arc=pass (i=1 spf=pass spfdomain=ti.com dkim=pass dkdomain=ti.com dmarc=pass fromdomain=ti.com); spf=pass (google.com: domain of linux-kernel+bounces-57278-ouuuleilei=gmail.com@vger.kernel.org designates 2604:1380:40f1:3f00::1 as permitted sender) smtp.mailfrom="linux-kernel+bounces-57278-ouuuleilei=gmail.com@vger.kernel.org"; dmarc=pass (p=QUARANTINE sp=NONE dis=NONE) header.from=ti.com Received: from smtp.subspace.kernel.org (wormhole.subspace.kernel.org [52.25.139.140]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by sy.mirrors.kernel.org (Postfix) with ESMTPS id C1635B22267 for <ouuuleilei@gmail.com>; Wed, 7 Feb 2024 22:56:59 +0000 (UTC) Received: from localhost.localdomain (localhost.localdomain [127.0.0.1]) by smtp.subspace.kernel.org (Postfix) with ESMTP id 594466A8B3; Wed, 7 Feb 2024 22:55:41 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=ti.com header.i=@ti.com header.b="DLyh20/s" Received: from fllv0015.ext.ti.com (fllv0015.ext.ti.com [198.47.19.141]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id C2A1E1EB42; Wed, 7 Feb 2024 22:55:36 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=198.47.19.141 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1707346538; cv=none; b=XN3BnkUJbjWOyt02HRb5KoIgVES4lMwiQyu0Pf+6KD1SVGb7hGgMw1plYabNWYbyMdwGhVmsVEh8ZouHRMHV71h+MRCBrGOgFnM32feqwqoE3vr+aJCotKhRNABJjTQeG6HWMiFR/agcrpd7jFZMyigAWE4FoakV/KmiBtFs7+8= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1707346538; c=relaxed/simple; bh=xX7JSbunBOvPlkFRAzytZEE8CRX45lbTaFkR1OIGUQQ=; h=From:To:CC:Subject:Date:Message-ID:MIME-Version:Content-Type; b=VvxrXdb9DPyMASH37MqIpcouL76uOj1+6a6fb8q3iRV92Chphf+KEzhSUFHSQ1pJeKSej9aL5uIb66IWdJ5k5ACTG5jISN4w3XumfBNHfMm1r/3snXOwOSeNr6+bkKFLorVEgu4U7jKQPKuVS0lmYsnA6KdBmXIAGIjLaqWf0+Q= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=ti.com; spf=pass smtp.mailfrom=ti.com; dkim=pass (1024-bit key) header.d=ti.com header.i=@ti.com header.b=DLyh20/s; arc=none smtp.client-ip=198.47.19.141 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=ti.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=ti.com Received: from fllv0035.itg.ti.com ([10.64.41.0]) by fllv0015.ext.ti.com (8.15.2/8.15.2) with ESMTP id 417MtR9h014810; Wed, 7 Feb 2024 16:55:27 -0600 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ti.com; s=ti-com-17Q1; t=1707346527; bh=zOoJZOLG26Ul8soZA3DhrVj70l4+Sl0iEM4P7gItmx8=; h=From:To:CC:Subject:Date; b=DLyh20/sL1Oy7AzPwimy0MAAp4SL98c1hF8vLtGNYdUORwO91VlsTegIdr62ZDZkP qUzOW9yGjRAJuf4Tsc30WFO8/qTQ4yuJoKbOEZxPb+5n02aLSC9mZhDy2JRmIuW3V4 ahXmUkZ4CNgmcLjM7G3XQuV9O8qqPWlfOu+Nv3Ss= Received: from DLEE110.ent.ti.com (dlee110.ent.ti.com [157.170.170.21]) by fllv0035.itg.ti.com (8.15.2/8.15.2) with ESMTPS id 417MtRuE082333 (version=TLSv1.2 cipher=AES256-GCM-SHA384 bits=256 verify=FAIL); Wed, 7 Feb 2024 16:55:27 -0600 Received: from DLEE102.ent.ti.com (157.170.170.32) by DLEE110.ent.ti.com (157.170.170.21) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.23; Wed, 7 Feb 2024 16:55:27 -0600 Received: from lelvsmtp6.itg.ti.com (10.180.75.249) by DLEE102.ent.ti.com (157.170.170.32) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.23 via Frontend Transport; Wed, 7 Feb 2024 16:55:27 -0600 Received: from judy-hp.dhcp.ti.com (judy-hp.dhcp.ti.com [128.247.81.105]) by lelvsmtp6.itg.ti.com (8.15.2/8.15.2) with ESMTP id 417MtQmT014027; Wed, 7 Feb 2024 16:55:26 -0600 From: Judith Mendez <jm@ti.com> To: Rob Herring <robh+dt@kernel.org>, Krzysztof Kozlowski <krzysztof.kozlowski+dt@linaro.org>, Conor Dooley <conor+dt@kernel.org> CC: Nishanth Menon <nm@ti.com>, Vignesh Raghavendra <vigneshr@ti.com>, Tero Kristo <kristo@kernel.org>, <linux-arm-kernel@lists.infradead.org>, <devicetree@vger.kernel.org>, <linux-kernel@vger.kernel.org> Subject: [PATCH v1 0/9] Fix MMC properties on Sitara devices Date: Wed, 7 Feb 2024 16:55:17 -0600 Message-ID: <20240207225526.3953230-1-jm@ti.com> X-Mailer: git-send-email 2.43.0 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: <linux-kernel.vger.kernel.org> List-Subscribe: <mailto:linux-kernel+subscribe@vger.kernel.org> List-Unsubscribe: <mailto:linux-kernel+unsubscribe@vger.kernel.org> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Content-Type: text/plain X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1790282695990244356 X-GMAIL-MSGID: 1790282695990244356 |
Series |
Fix MMC properties on Sitara devices
|
|
Message
Judith Mendez
Feb. 7, 2024, 10:55 p.m. UTC
This patch series aims to add or fix MMC properties: OTAPDLY/ITAPDLY. The DLL properties ti,trm-icp and ti,driver-strength-ohm should also be updated since only AM64x and AM62p devices have a DLL to enable, so remove these properties when not applicable. Also add support for eMMC on AM62ax platform. This series was tested on: - AM62a SK - AM62x SK - AM62p SK - AM64x GP EVM - AM64x SK EVM Judith Mendez (7): arm64: dts: ti: k3-am62a-main: Add sdhci2 instance arm64: dts: ti: k3-am64-main: Fix ITAP/OTAP values for MMC arm64: dts: ti: k3-am62p: Add ITAP/OTAP values for MMC arm64: dts: ti: k3-am6*: Remove DLL properties for soft PHYs arm64: dts: ti: k3-am6*: Fix ti,clkbuf-sel property in MMC nodes arm64: dts: ti: k3-am6*: Fix bus-width property in MMC nodes arm64: dts: ti: k3-am6*: Fix bootph-all property in MMC node Nitin Yadav (2): arm64: dts: ti: k3-am62a-main: Add sdhci0 instance arm64: dts: ti: k3-am62a7-sk: Enable eMMC support arch/arm64/boot/dts/ti/k3-am62-main.dtsi | 12 +++-- .../arm64/boot/dts/ti/k3-am625-beagleplay.dts | 4 -- arch/arm64/boot/dts/ti/k3-am62a-main.dtsi | 45 ++++++++++++++++++- arch/arm64/boot/dts/ti/k3-am62a7-sk.dts | 27 ++++++++++- arch/arm64/boot/dts/ti/k3-am62p-main.dtsi | 44 ++++++++++++++++-- arch/arm64/boot/dts/ti/k3-am62p5-sk.dts | 5 +-- .../arm64/boot/dts/ti/k3-am62x-sk-common.dtsi | 2 - arch/arm64/boot/dts/ti/k3-am64-main.dtsi | 15 +++++-- arch/arm64/boot/dts/ti/k3-am642-evm.dts | 4 +- arch/arm64/boot/dts/ti/k3-am642-sk.dts | 2 - 10 files changed, 130 insertions(+), 30 deletions(-) base-commit: 1e6bbc5185bcd113c8d2f7aa0a02f588a6bdbe5d
Comments
Hello Judith and TI folks, On Wed, Feb 07, 2024 at 04:55:17PM -0600, Judith Mendez wrote: > This patch series aims to add or fix MMC properties: > OTAPDLY/ITAPDLY. > > The DLL properties ti,trm-icp and ti,driver-strength-ohm > should also be updated since only AM64x and AM62p devices > have a DLL to enable, so remove these properties when not > applicable. Do you have any reference regarding this change? TI reference manual or anything like that? No change needed in sdhci_am654.c? It seems that `drv_strength` is written to some register unconditionally, is it ok to do so? Do this change implies that there is no way to configure the drive strength on such SoCs and MMC/SD trace impedance must be the nominal 50ohm? Thanks, Francesco
Hi Francesco, On 2/11/24 9:44 AM, Francesco Dolcini wrote: > Hello Judith and TI folks, > > On Wed, Feb 07, 2024 at 04:55:17PM -0600, Judith Mendez wrote: >> This patch series aims to add or fix MMC properties: >> OTAPDLY/ITAPDLY. >> >> The DLL properties ti,trm-icp and ti,driver-strength-ohm >> should also be updated since only AM64x and AM62p devices >> have a DLL to enable, so remove these properties when not >> applicable. > > Do you have any reference regarding this change? TI reference manual or > anything like that? I believe there is no specific documentation that states outright that these device tree properties are not applicable for devices like AM62x. There are a few hints in the device datasheet and TRM, if the MMC PHY has a DLL to enable, DLL properties should show in both docs. Also, you can read the MMC bindings doc description: https://github.com/torvalds/linux/blob/master/Documentation/devicetree /bindings/mmc/sdhci-am654.yaml#L179 > > No change needed in sdhci_am654.c? It seems that `drv_strength` is written > to some register unconditionally, is it ok to do so? Actually, we only write this value to the register if there is a DLL to enable. If we have this property in device tree for devices like AM62x and AM62ax, this property is ignored in the driver. So I am removing this property from device tree as part of the effort to clean up MMC nodes in device tree. > > Do this change implies that there is no way to configure the drive > strength on such SoCs and MMC/SD trace impedance must be the nominal > 50ohm? We do not support changing drive strength for these devices. My understanding is that the drive strength should default to about 40 ohms, which should be good enough for any eMMC operating mode. ~ Judith > > Thanks, > Francesco >