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The new algorithm should be used when delay chain is enabled. The ITAPDLY is selected from the largest passing window and the buffer is not viewed as a circular buffer. The new tuning algorithm is implemented as per the paper published here [0] and has been tested on the following platforms: AM62x SK, AM62A SK, AM62p SK, AM64x SK, and AM64x EVM. The series also includes a few fixes in the sdhci_am654 driver on OTAPDLYEN/ITAPDLYEN and ITAPDELSEL. Changelog: v1->v2: - Remove unnecessary indentations and if/else in sdhci_am654_calculate_itap - Optimize sdhci_am654_calculate_itap() - Call sdhci_am654_write_itapdly() in sdhci_am654_set_clock() instead of sdhci_am654_setup_dll() - Change otap_del_sel[], itap_del_sel[], and itap_del_ena[] to type u32 - Revert unnecessary reformating in sdhci_am654_set_clock() and sdhci_j721e_4bit_set_clock() Judith Mendez (7): mmc: sdhci_am654: Add tuning algorithm for delay chain mmc: sdhci_am654: Write ITAPDLY for DDR52 timing mmc: sdhci_am654: Add missing OTAP/ITAP enable mmc: sdhci_am654: Fix itapdly/otapdly array type mmc: sdhci_am654: Update comments in sdhci_am654_set_clock mmc: sdhci_am654: Add ITAPDLYSEL in sdhci_j721e_4bit_set_clock mmc: sdhci_am654: Fix ITAPDLY for HS400 timing drivers/mmc/host/sdhci_am654.c | 176 ++++++++++++++++++++++++++------- 1 file changed, 138 insertions(+), 38 deletions(-) base-commit: 40d83f40c44ba8aa79cba409ace619db3a7f86f2