mbox series

[v2,0/7] Add tuning algorithm for delay chain

Message ID 20240207011520.3128382-1-jm@ti.com
Headers
Series Add tuning algorithm for delay chain |

Message

Judith Mendez Feb. 7, 2024, 1:15 a.m. UTC 
  This patch series introduces a new tuning algorithm for
mmc. The new algorithm should be used when delay chain is
enabled. The ITAPDLY is selected from the largest passing
window and the buffer is not viewed as a circular buffer.
The new tuning algorithm is implemented as per the paper
published here [0] and has been tested on the following
platforms: AM62x SK, AM62A SK, AM62p SK, AM64x SK, and AM64x
EVM.

The series also includes a few fixes in the sdhci_am654
driver on OTAPDLYEN/ITAPDLYEN and ITAPDELSEL.

Changelog:
v1->v2:
- Remove unnecessary indentations and if/else in
 sdhci_am654_calculate_itap
- Optimize sdhci_am654_calculate_itap()
- Call sdhci_am654_write_itapdly() in sdhci_am654_set_clock()
 instead of sdhci_am654_setup_dll()
- Change otap_del_sel[], itap_del_sel[], and itap_del_ena[]
 to type u32
- Revert unnecessary reformating in sdhci_am654_set_clock()
 and sdhci_j721e_4bit_set_clock()

Judith Mendez (7):
  mmc: sdhci_am654: Add tuning algorithm for delay chain
  mmc: sdhci_am654: Write ITAPDLY for DDR52 timing
  mmc: sdhci_am654: Add missing OTAP/ITAP enable
  mmc: sdhci_am654: Fix itapdly/otapdly array type
  mmc: sdhci_am654: Update comments in sdhci_am654_set_clock
  mmc: sdhci_am654: Add ITAPDLYSEL in sdhci_j721e_4bit_set_clock
  mmc: sdhci_am654: Fix ITAPDLY for HS400 timing

 drivers/mmc/host/sdhci_am654.c | 176 ++++++++++++++++++++++++++-------
 1 file changed, 138 insertions(+), 38 deletions(-)


base-commit: 40d83f40c44ba8aa79cba409ace619db3a7f86f2

Comments

Francesco Dolcini Feb. 11, 2024, 4:02 p.m. UTC | #1 
On Tue, Feb 06, 2024 at 07:15:13PM -0600, Judith Mendez wrote:
> This patch series introduces a new tuning algorithm for
> mmc. The new algorithm should be used when delay chain is
> enabled. The ITAPDLY is selected from the largest passing
> window and the buffer is not viewed as a circular buffer.
> The new tuning algorithm is implemented as per the paper
> published here [0] and has been tested on the following

Where is this `[0]`?

> platforms: AM62x SK, AM62A SK, AM62p SK, AM64x SK, and AM64x
> EVM.

In the other patches you link some document, but I was not able to find
anything related to AM62, can you provide some reference on this
specific SOC?

Francesco
Judith Mendez Feb. 12, 2024, 4:33 p.m. UTC | #2 
Hi Francesco,

On 2/11/24 10:02 AM, Francesco Dolcini wrote:
> On Tue, Feb 06, 2024 at 07:15:13PM -0600, Judith Mendez wrote:
>> This patch series introduces a new tuning algorithm for
>> mmc. The new algorithm should be used when delay chain is
>> enabled. The ITAPDLY is selected from the largest passing
>> window and the buffer is not viewed as a circular buffer.
>> The new tuning algorithm is implemented as per the paper
>> published here [0] and has been tested on the following
> 
> Where is this `[0]`?

I must have missed linking the ref doc here, will add in next
iteration, thanks.

> 
>> platforms: AM62x SK, AM62A SK, AM62p SK, AM64x SK, and AM64x
>> EVM.
> 
> In the other patches you link some document, but I was not able to find
> anything related to AM62, can you provide some reference on this
> specific SOC?

This patch series fixes issues that affect all Sitara SoCs, not only
AM62x. However, I could use AM62x for reference, no problem.

> 
> Francesco
> 

~ Judith
Francesco Dolcini Feb. 12, 2024, 5:32 p.m. UTC | #3 
Hi Judith,

On Mon, Feb 12, 2024 at 10:33:35AM -0600, Judith Mendez wrote:
> Hi Francesco,
> 
> On 2/11/24 10:02 AM, Francesco Dolcini wrote:
> > On Tue, Feb 06, 2024 at 07:15:13PM -0600, Judith Mendez wrote:
> > > This patch series introduces a new tuning algorithm for
> > > mmc. The new algorithm should be used when delay chain is
> > > enabled. The ITAPDLY is selected from the largest passing
> > > window and the buffer is not viewed as a circular buffer.
> > > The new tuning algorithm is implemented as per the paper
> > > published here [0] and has been tested on the following
> > 
> > Where is this `[0]`?
> 
> I must have missed linking the ref doc here, will add in next
> iteration, thanks.
> 
> > 
> > > platforms: AM62x SK, AM62A SK, AM62p SK, AM64x SK, and AM64x
> > > EVM.
> > 
> > In the other patches you link some document, but I was not able to find
> > anything related to AM62, can you provide some reference on this
> > specific SOC?
> 
> This patch series fixes issues that affect all Sitara SoCs, not only
> AM62x. However, I could use AM62x for reference, no problem.

I am really looking for documentation here that is related to the AM62
because I was not able to find anything and this is a topic of interest
for me.

Can you share something?

Francesco
Judith Mendez Feb. 12, 2024, 5:56 p.m. UTC | #4 
Hi Francesco,

On 2/12/24 11:32 AM, Francesco Dolcini wrote:
> Hi Judith,
> 
> On Mon, Feb 12, 2024 at 10:33:35AM -0600, Judith Mendez wrote:
>> Hi Francesco,
>>
>> On 2/11/24 10:02 AM, Francesco Dolcini wrote:
>>> On Tue, Feb 06, 2024 at 07:15:13PM -0600, Judith Mendez wrote:
>>>> This patch series introduces a new tuning algorithm for
>>>> mmc. The new algorithm should be used when delay chain is
>>>> enabled. The ITAPDLY is selected from the largest passing
>>>> window and the buffer is not viewed as a circular buffer.
>>>> The new tuning algorithm is implemented as per the paper
>>>> published here [0] and has been tested on the following
>>>
>>> Where is this `[0]`?
>>
>> I must have missed linking the ref doc here, will add in next
>> iteration, thanks.
>>
>>>
>>>> platforms: AM62x SK, AM62A SK, AM62p SK, AM64x SK, and AM64x
>>>> EVM.
>>>
>>> In the other patches you link some document, but I was not able to find
>>> anything related to AM62, can you provide some reference on this
>>> specific SOC?
>>
>> This patch series fixes issues that affect all Sitara SoCs, not only
>> AM62x. However, I could use AM62x for reference, no problem.
> 
> I am really looking for documentation here that is related to the AM62
> because I was not able to find anything and this is a topic of interest
> for me.
> 

The AM62x device datasheet: https://www.ti.com/lit/ds/symlink/am625.pdf,
reference Table 7-79 for MMC0 and Table 7-97 for MMC1.

TRM, reference section 12.4.5 for MMCSD and section 12.4.5.5.2.3.2
Tuning Sequence that we currently implement in the sdhci_am654 driver.
Section 14.8.4.6 for MMCSD registers, SS_CFG_PHY_CTRL_1,
SS_CFG_PHY_CTRL_5, and SS_CFG_PHY_CTRL_5 are usually of higher interest.

Tuning algorithm, reference: 
https://www.ti.com/lit/an/spract9/spract9.pdf which is applicable for 
AM62x, DLL is not applicable
for AM62x, so the tuning algorithm should not consider the buffer
as a circular buffer.

~ Judith

> Can you share something?
> 
> Francesco
>