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[v10,00/14] PCI: imx6: Clean up and add imx95 pci support

Message ID 20240205173335.1120469-1-Frank.Li@nxp.com
Headers
Series PCI: imx6: Clean up and add imx95 pci support |

Message

Frank Li Feb. 5, 2024, 5:33 p.m. UTC 
  first 6 patches use drvdata: flags to simplify some switch-case code.
Improve maintaince and easy to read code.

Then add imx95 basic pci host function.

follow two patch do endpoint code clean up.
Then add imx95 basic endpont function.

Compared with v2, added EP function support and some fixes,  please change
notes at each patches.

Change from v9 to v10
- remove two patches:
>   dt-bindings: imx6q-pcie: Add linux,pci-domain as required for iMX8MQ
>   PCI: imx6: Using "linux,pci-domain" as slot ID
it is not good solution to fixed hardcode check to get controller id.
Will see better solution later.

dt-binding pass pcie node:

pcie0: pcie@4c300000 {
                        compatible = "fsl,imx95-pcie";
                        reg = <0 0x4c300000 0 0x40000>,
                                <0 0x4c360000 0 0x10000>,
                                <0 0x4c340000 0 0x20000>,
                                <0 0x60100000 0 0xfe00000>;
                        reg-names = "dbi", "atu", "app", "config";
                        #address-cells = <3>;
                        #size-cells = <2>;
                        device_type = "pci";
                        linux,pci-domain = <0>;
                        bus-range = <0x00 0xff>;
                        ranges = <0x81000000 0x0 0x00000000 0x0 0x6ff00000 0 0x00100000>,
                                 <0x82000000 0x0 0x10000000 0x9 0x10000000 0 0x10000000>;
                        num-lanes = <1>;
                        num-viewport = <8>;
                        interrupts = <GIC_SPI 310 IRQ_TYPE_LEVEL_HIGH>;
                        interrupt-names = "msi";
                        #interrupt-cells = <1>;
                        interrupt-map-mask = <0 0 0 0x7>;
                        interrupt-map = <0 0 0 1 &gic 0 0 GIC_SPI 309 IRQ_TYPE_LEVEL_HIGH>,
                                        <0 0 0 2 &gic 0 0 GIC_SPI 308 IRQ_TYPE_LEVEL_HIGH>,
                                        <0 0 0 3 &gic 0 0 GIC_SPI 307 IRQ_TYPE_LEVEL_HIGH>,
                                        <0 0 0 4 &gic 0 0 GIC_SPI 306 IRQ_TYPE_LEVEL_HIGH>;
                        fsl,max-link-speed = <3>;
                        clocks = <&scmi_clk IMX95_CLK_HSIO>,
                                 <&scmi_clk IMX95_CLK_HSIOPLL>,
                                 <&scmi_clk IMX95_CLK_HSIOPLL_VCO>,
                                 <&scmi_clk IMX95_CLK_HSIOPCIEAUX>;
                        clock-names = "pcie", "pcie_bus", "pcie_phy", "pcie_aux";
                        assigned-clocks =<&scmi_clk IMX95_CLK_HSIOPLL_VCO>,
                                         <&scmi_clk IMX95_CLK_HSIOPLL>,
                                         <&scmi_clk IMX95_CLK_HSIOPCIEAUX>;
                        assigned-clock-rates = <3600000000>, <100000000>, <10000000>;
                        assigned-clock-parents = <0>, <0>,
                                                 <&scmi_clk IMX95_CLK_SYSPLL1_PFD1_DIV2>;
                        power-domains = <&scmi_devpd IMX95_PD_HSIO_TOP>;
                        /* 0x30~0x37 stream id for pci0 */
                        /*
                         * iommu-map = <0x000 &apps_smmu 0x30 0x1>,
                         * <0x100 &apps_smmu 0x31 0x1>;
                         */
                        status = "disabled";
                };

pcie1: pcie-ep@4c380000 {
                        compatible = "fsl,imx95-pcie-ep";
                        reg = <0 0x4c380000 0 0x20000>,
                              <0 0x4c3e0000 0 0x1000>,
                              <0 0x4c3a0000 0 0x1000>,
                              <0 0x4c3c0000 0 0x10000>,
                              <0 0x4c3f0000 0 0x10000>,
                              <0xa 0 1 0>;
                        reg-names = "dbi", "atu", "dbi2", "app", "dma", "addr_space";
                        interrupts = <GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH>;
                        interrupt-names = "dma";
                        fsl,max-link-speed = <3>;
                        clocks = <&scmi_clk IMX95_CLK_HSIO>,
                                 <&scmi_clk IMX95_CLK_HSIOPLL>,
                                 <&scmi_clk IMX95_CLK_HSIOPLL_VCO>,
                                 <&scmi_clk IMX95_CLK_HSIOPCIEAUX>;
                        clock-names = "pcie", "pcie_bus", "pcie_phy", "pcie_aux";
                        assigned-clocks =<&scmi_clk IMX95_CLK_HSIOPLL_VCO>,
                                         <&scmi_clk IMX95_CLK_HSIOPLL>,
                                         <&scmi_clk IMX95_CLK_HSIOPCIEAUX>;
                        assigned-clock-rates = <3600000000>, <100000000>, <10000000>;
                        assigned-clock-parents = <0>, <0>,
                                                 <&scmi_clk IMX95_CLK_SYSPLL1_PFD1_DIV2>;
                        power-domains = <&scmi_devpd IMX95_PD_HSIO_TOP>;
                        status = "disabled";
                };

Frank Li (13):
  PCI: imx6: Simplify clock handling by using clk_bulk*() function
  PCI: imx6: Simplify phy handling by using IMX6_PCIE_FLAG_HAS_PHYDRV
  PCI: imx6: Simplify reset handling by using by using
    *_FLAG_HAS_*_RESET
  PCI: imx6: Simplify ltssm_enable() by using ltssm_off and ltssm_mask
  PCI: imx6: Simplify configure_type() by using mode_off and mode_mask
  PCI: imx6: Simplify switch-case logic by involve init_phy callback
  dt-bindings: imx6q-pcie: Clean up irrationality clocks check
  dt-bindings: imx6q-pcie: Restruct reg and reg-name
  PCI: imx6: Add iMX95 PCIe Root Complex support
  PCI: imx6: Clean up get addr_space code
  PCI: imx6: Add epc_features in imx6_pcie_drvdata
  dt-bindings: imx6q-pcie: Add iMX95 pcie endpoint compatible string
  PCI: imx6: Add iMX95 Endpoint (EP) support

Richard Zhu (1):
  dt-bindings: imx6q-pcie: Add imx95 pcie compatible string

 .../bindings/pci/fsl,imx6q-pcie-common.yaml   |  17 +-
 .../bindings/pci/fsl,imx6q-pcie-ep.yaml       |  46 +-
 .../bindings/pci/fsl,imx6q-pcie.yaml          |  49 +-
 drivers/pci/controller/dwc/pci-imx6.c         | 634 ++++++++++--------
 4 files changed, 436 insertions(+), 310 deletions(-)

Comments

Frank Li Feb. 19, 2024, 3:11 p.m. UTC | #1 
On Mon, Feb 05, 2024 at 12:33:21PM -0500, Frank Li wrote:
> first 6 patches use drvdata: flags to simplify some switch-case code.
> Improve maintaince and easy to read code.
> 

@Lorenzo Pieralisi:

	Do you have chance to look other patches?
	Mani's apply EP side change. 
	'PCI: imx6: Add iMX95 Endpoint (EP) support' need be rebased. 

Frank

> Then add imx95 basic pci host function.
> 
> follow two patch do endpoint code clean up.
> Then add imx95 basic endpont function.
> 
> Compared with v2, added EP function support and some fixes,  please change
> notes at each patches.
> 
> Change from v9 to v10
> - remove two patches:
> >   dt-bindings: imx6q-pcie: Add linux,pci-domain as required for iMX8MQ
> >   PCI: imx6: Using "linux,pci-domain" as slot ID
> it is not good solution to fixed hardcode check to get controller id.
> Will see better solution later.
> 
> dt-binding pass pcie node:
> 
> pcie0: pcie@4c300000 {
>                         compatible = "fsl,imx95-pcie";
>                         reg = <0 0x4c300000 0 0x40000>,
>                                 <0 0x4c360000 0 0x10000>,
>                                 <0 0x4c340000 0 0x20000>,
>                                 <0 0x60100000 0 0xfe00000>;
>                         reg-names = "dbi", "atu", "app", "config";
>                         #address-cells = <3>;
>                         #size-cells = <2>;
>                         device_type = "pci";
>                         linux,pci-domain = <0>;
>                         bus-range = <0x00 0xff>;
>                         ranges = <0x81000000 0x0 0x00000000 0x0 0x6ff00000 0 0x00100000>,
>                                  <0x82000000 0x0 0x10000000 0x9 0x10000000 0 0x10000000>;
>                         num-lanes = <1>;
>                         num-viewport = <8>;
>                         interrupts = <GIC_SPI 310 IRQ_TYPE_LEVEL_HIGH>;
>                         interrupt-names = "msi";
>                         #interrupt-cells = <1>;
>                         interrupt-map-mask = <0 0 0 0x7>;
>                         interrupt-map = <0 0 0 1 &gic 0 0 GIC_SPI 309 IRQ_TYPE_LEVEL_HIGH>,
>                                         <0 0 0 2 &gic 0 0 GIC_SPI 308 IRQ_TYPE_LEVEL_HIGH>,
>                                         <0 0 0 3 &gic 0 0 GIC_SPI 307 IRQ_TYPE_LEVEL_HIGH>,
>                                         <0 0 0 4 &gic 0 0 GIC_SPI 306 IRQ_TYPE_LEVEL_HIGH>;
>                         fsl,max-link-speed = <3>;
>                         clocks = <&scmi_clk IMX95_CLK_HSIO>,
>                                  <&scmi_clk IMX95_CLK_HSIOPLL>,
>                                  <&scmi_clk IMX95_CLK_HSIOPLL_VCO>,
>                                  <&scmi_clk IMX95_CLK_HSIOPCIEAUX>;
>                         clock-names = "pcie", "pcie_bus", "pcie_phy", "pcie_aux";
>                         assigned-clocks =<&scmi_clk IMX95_CLK_HSIOPLL_VCO>,
>                                          <&scmi_clk IMX95_CLK_HSIOPLL>,
>                                          <&scmi_clk IMX95_CLK_HSIOPCIEAUX>;
>                         assigned-clock-rates = <3600000000>, <100000000>, <10000000>;
>                         assigned-clock-parents = <0>, <0>,
>                                                  <&scmi_clk IMX95_CLK_SYSPLL1_PFD1_DIV2>;
>                         power-domains = <&scmi_devpd IMX95_PD_HSIO_TOP>;
>                         /* 0x30~0x37 stream id for pci0 */
>                         /*
>                          * iommu-map = <0x000 &apps_smmu 0x30 0x1>,
>                          * <0x100 &apps_smmu 0x31 0x1>;
>                          */
>                         status = "disabled";
>                 };
> 
> pcie1: pcie-ep@4c380000 {
>                         compatible = "fsl,imx95-pcie-ep";
>                         reg = <0 0x4c380000 0 0x20000>,
>                               <0 0x4c3e0000 0 0x1000>,
>                               <0 0x4c3a0000 0 0x1000>,
>                               <0 0x4c3c0000 0 0x10000>,
>                               <0 0x4c3f0000 0 0x10000>,
>                               <0xa 0 1 0>;
>                         reg-names = "dbi", "atu", "dbi2", "app", "dma", "addr_space";
>                         interrupts = <GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH>;
>                         interrupt-names = "dma";
>                         fsl,max-link-speed = <3>;
>                         clocks = <&scmi_clk IMX95_CLK_HSIO>,
>                                  <&scmi_clk IMX95_CLK_HSIOPLL>,
>                                  <&scmi_clk IMX95_CLK_HSIOPLL_VCO>,
>                                  <&scmi_clk IMX95_CLK_HSIOPCIEAUX>;
>                         clock-names = "pcie", "pcie_bus", "pcie_phy", "pcie_aux";
>                         assigned-clocks =<&scmi_clk IMX95_CLK_HSIOPLL_VCO>,
>                                          <&scmi_clk IMX95_CLK_HSIOPLL>,
>                                          <&scmi_clk IMX95_CLK_HSIOPCIEAUX>;
>                         assigned-clock-rates = <3600000000>, <100000000>, <10000000>;
>                         assigned-clock-parents = <0>, <0>,
>                                                  <&scmi_clk IMX95_CLK_SYSPLL1_PFD1_DIV2>;
>                         power-domains = <&scmi_devpd IMX95_PD_HSIO_TOP>;
>                         status = "disabled";
>                 };
> 
> Frank Li (13):
>   PCI: imx6: Simplify clock handling by using clk_bulk*() function
>   PCI: imx6: Simplify phy handling by using IMX6_PCIE_FLAG_HAS_PHYDRV
>   PCI: imx6: Simplify reset handling by using by using
>     *_FLAG_HAS_*_RESET
>   PCI: imx6: Simplify ltssm_enable() by using ltssm_off and ltssm_mask
>   PCI: imx6: Simplify configure_type() by using mode_off and mode_mask
>   PCI: imx6: Simplify switch-case logic by involve init_phy callback
>   dt-bindings: imx6q-pcie: Clean up irrationality clocks check
>   dt-bindings: imx6q-pcie: Restruct reg and reg-name
>   PCI: imx6: Add iMX95 PCIe Root Complex support
>   PCI: imx6: Clean up get addr_space code
>   PCI: imx6: Add epc_features in imx6_pcie_drvdata
>   dt-bindings: imx6q-pcie: Add iMX95 pcie endpoint compatible string
>   PCI: imx6: Add iMX95 Endpoint (EP) support
> 
> Richard Zhu (1):
>   dt-bindings: imx6q-pcie: Add imx95 pcie compatible string
> 
>  .../bindings/pci/fsl,imx6q-pcie-common.yaml   |  17 +-
>  .../bindings/pci/fsl,imx6q-pcie-ep.yaml       |  46 +-
>  .../bindings/pci/fsl,imx6q-pcie.yaml          |  49 +-
>  drivers/pci/controller/dwc/pci-imx6.c         | 634 ++++++++++--------
>  4 files changed, 436 insertions(+), 310 deletions(-)
> 
> -- 
> 2.34.1
>
Lorenzo Pieralisi Feb. 19, 2024, 3:21 p.m. UTC | #2 
On Mon, Feb 19, 2024 at 10:11:45AM -0500, Frank Li wrote:
> On Mon, Feb 05, 2024 at 12:33:21PM -0500, Frank Li wrote:
> > first 6 patches use drvdata: flags to simplify some switch-case code.
> > Improve maintaince and easy to read code.
> > 
> 
> @Lorenzo Pieralisi:
> 
> 	Do you have chance to look other patches?

Yes, they are fine.

> 	Mani's apply EP side change. 
> 	'PCI: imx6: Add iMX95 Endpoint (EP) support' need be rebased. 

What does that mean ? I think it is best to pull the series in a single
branch if there are not any dependencies on other branches.

Thanks,
Lorenzo

> Frank
> 
> > Then add imx95 basic pci host function.
> > 
> > follow two patch do endpoint code clean up.
> > Then add imx95 basic endpont function.
> > 
> > Compared with v2, added EP function support and some fixes,  please change
> > notes at each patches.
> > 
> > Change from v9 to v10
> > - remove two patches:
> > >   dt-bindings: imx6q-pcie: Add linux,pci-domain as required for iMX8MQ
> > >   PCI: imx6: Using "linux,pci-domain" as slot ID
> > it is not good solution to fixed hardcode check to get controller id.
> > Will see better solution later.
> > 
> > dt-binding pass pcie node:
> > 
> > pcie0: pcie@4c300000 {
> >                         compatible = "fsl,imx95-pcie";
> >                         reg = <0 0x4c300000 0 0x40000>,
> >                                 <0 0x4c360000 0 0x10000>,
> >                                 <0 0x4c340000 0 0x20000>,
> >                                 <0 0x60100000 0 0xfe00000>;
> >                         reg-names = "dbi", "atu", "app", "config";
> >                         #address-cells = <3>;
> >                         #size-cells = <2>;
> >                         device_type = "pci";
> >                         linux,pci-domain = <0>;
> >                         bus-range = <0x00 0xff>;
> >                         ranges = <0x81000000 0x0 0x00000000 0x0 0x6ff00000 0 0x00100000>,
> >                                  <0x82000000 0x0 0x10000000 0x9 0x10000000 0 0x10000000>;
> >                         num-lanes = <1>;
> >                         num-viewport = <8>;
> >                         interrupts = <GIC_SPI 310 IRQ_TYPE_LEVEL_HIGH>;
> >                         interrupt-names = "msi";
> >                         #interrupt-cells = <1>;
> >                         interrupt-map-mask = <0 0 0 0x7>;
> >                         interrupt-map = <0 0 0 1 &gic 0 0 GIC_SPI 309 IRQ_TYPE_LEVEL_HIGH>,
> >                                         <0 0 0 2 &gic 0 0 GIC_SPI 308 IRQ_TYPE_LEVEL_HIGH>,
> >                                         <0 0 0 3 &gic 0 0 GIC_SPI 307 IRQ_TYPE_LEVEL_HIGH>,
> >                                         <0 0 0 4 &gic 0 0 GIC_SPI 306 IRQ_TYPE_LEVEL_HIGH>;
> >                         fsl,max-link-speed = <3>;
> >                         clocks = <&scmi_clk IMX95_CLK_HSIO>,
> >                                  <&scmi_clk IMX95_CLK_HSIOPLL>,
> >                                  <&scmi_clk IMX95_CLK_HSIOPLL_VCO>,
> >                                  <&scmi_clk IMX95_CLK_HSIOPCIEAUX>;
> >                         clock-names = "pcie", "pcie_bus", "pcie_phy", "pcie_aux";
> >                         assigned-clocks =<&scmi_clk IMX95_CLK_HSIOPLL_VCO>,
> >                                          <&scmi_clk IMX95_CLK_HSIOPLL>,
> >                                          <&scmi_clk IMX95_CLK_HSIOPCIEAUX>;
> >                         assigned-clock-rates = <3600000000>, <100000000>, <10000000>;
> >                         assigned-clock-parents = <0>, <0>,
> >                                                  <&scmi_clk IMX95_CLK_SYSPLL1_PFD1_DIV2>;
> >                         power-domains = <&scmi_devpd IMX95_PD_HSIO_TOP>;
> >                         /* 0x30~0x37 stream id for pci0 */
> >                         /*
> >                          * iommu-map = <0x000 &apps_smmu 0x30 0x1>,
> >                          * <0x100 &apps_smmu 0x31 0x1>;
> >                          */
> >                         status = "disabled";
> >                 };
> > 
> > pcie1: pcie-ep@4c380000 {
> >                         compatible = "fsl,imx95-pcie-ep";
> >                         reg = <0 0x4c380000 0 0x20000>,
> >                               <0 0x4c3e0000 0 0x1000>,
> >                               <0 0x4c3a0000 0 0x1000>,
> >                               <0 0x4c3c0000 0 0x10000>,
> >                               <0 0x4c3f0000 0 0x10000>,
> >                               <0xa 0 1 0>;
> >                         reg-names = "dbi", "atu", "dbi2", "app", "dma", "addr_space";
> >                         interrupts = <GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH>;
> >                         interrupt-names = "dma";
> >                         fsl,max-link-speed = <3>;
> >                         clocks = <&scmi_clk IMX95_CLK_HSIO>,
> >                                  <&scmi_clk IMX95_CLK_HSIOPLL>,
> >                                  <&scmi_clk IMX95_CLK_HSIOPLL_VCO>,
> >                                  <&scmi_clk IMX95_CLK_HSIOPCIEAUX>;
> >                         clock-names = "pcie", "pcie_bus", "pcie_phy", "pcie_aux";
> >                         assigned-clocks =<&scmi_clk IMX95_CLK_HSIOPLL_VCO>,
> >                                          <&scmi_clk IMX95_CLK_HSIOPLL>,
> >                                          <&scmi_clk IMX95_CLK_HSIOPCIEAUX>;
> >                         assigned-clock-rates = <3600000000>, <100000000>, <10000000>;
> >                         assigned-clock-parents = <0>, <0>,
> >                                                  <&scmi_clk IMX95_CLK_SYSPLL1_PFD1_DIV2>;
> >                         power-domains = <&scmi_devpd IMX95_PD_HSIO_TOP>;
> >                         status = "disabled";
> >                 };
> > 
> > Frank Li (13):
> >   PCI: imx6: Simplify clock handling by using clk_bulk*() function
> >   PCI: imx6: Simplify phy handling by using IMX6_PCIE_FLAG_HAS_PHYDRV
> >   PCI: imx6: Simplify reset handling by using by using
> >     *_FLAG_HAS_*_RESET
> >   PCI: imx6: Simplify ltssm_enable() by using ltssm_off and ltssm_mask
> >   PCI: imx6: Simplify configure_type() by using mode_off and mode_mask
> >   PCI: imx6: Simplify switch-case logic by involve init_phy callback
> >   dt-bindings: imx6q-pcie: Clean up irrationality clocks check
> >   dt-bindings: imx6q-pcie: Restruct reg and reg-name
> >   PCI: imx6: Add iMX95 PCIe Root Complex support
> >   PCI: imx6: Clean up get addr_space code
> >   PCI: imx6: Add epc_features in imx6_pcie_drvdata
> >   dt-bindings: imx6q-pcie: Add iMX95 pcie endpoint compatible string
> >   PCI: imx6: Add iMX95 Endpoint (EP) support
> > 
> > Richard Zhu (1):
> >   dt-bindings: imx6q-pcie: Add imx95 pcie compatible string
> > 
> >  .../bindings/pci/fsl,imx6q-pcie-common.yaml   |  17 +-
> >  .../bindings/pci/fsl,imx6q-pcie-ep.yaml       |  46 +-
> >  .../bindings/pci/fsl,imx6q-pcie.yaml          |  49 +-
> >  drivers/pci/controller/dwc/pci-imx6.c         | 634 ++++++++++--------
> >  4 files changed, 436 insertions(+), 310 deletions(-)
> > 
> > -- 
> > 2.34.1
> >
Frank Li Feb. 19, 2024, 3:34 p.m. UTC | #3 
On Mon, Feb 19, 2024 at 04:21:26PM +0100, Lorenzo Pieralisi wrote:
> On Mon, Feb 19, 2024 at 10:11:45AM -0500, Frank Li wrote:
> > On Mon, Feb 05, 2024 at 12:33:21PM -0500, Frank Li wrote:
> > > first 6 patches use drvdata: flags to simplify some switch-case code.
> > > Improve maintaince and easy to read code.
> > > 
> > 
> > @Lorenzo Pieralisi:
> > 
> > 	Do you have chance to look other patches?
> 
> Yes, they are fine.
> 
> > 	Mani's apply EP side change. 
> > 	'PCI: imx6: Add iMX95 Endpoint (EP) support' need be rebased. 
> 
> What does that mean ? I think it is best to pull the series in a single
> branch if there are not any dependencies on other branches.

Two options:

Options 1:
	Merge 1-13. Left 'PCI: imx6: Add iMX95 Endpoint (EP) support'.
I will send out later with other clean up patches.

Options 2:
	I rebase to https://git.kernel.org/pub/scm/linux/kernel/git/pci/pci.git/log/?h=endpoint
	After Bjorn Helgaas merge to next, you can pick all.

I perfer opitons 1.

Frank

> 
> Thanks,
> Lorenzo
> 
> > Frank
> > 
> > > Then add imx95 basic pci host function.
> > > 
> > > follow two patch do endpoint code clean up.
> > > Then add imx95 basic endpont function.
> > > 
> > > Compared with v2, added EP function support and some fixes,  please change
> > > notes at each patches.
> > > 
> > > Change from v9 to v10
> > > - remove two patches:
> > > >   dt-bindings: imx6q-pcie: Add linux,pci-domain as required for iMX8MQ
> > > >   PCI: imx6: Using "linux,pci-domain" as slot ID
> > > it is not good solution to fixed hardcode check to get controller id.
> > > Will see better solution later.
> > > 
> > > dt-binding pass pcie node:
> > > 
> > > pcie0: pcie@4c300000 {
> > >                         compatible = "fsl,imx95-pcie";
> > >                         reg = <0 0x4c300000 0 0x40000>,
> > >                                 <0 0x4c360000 0 0x10000>,
> > >                                 <0 0x4c340000 0 0x20000>,
> > >                                 <0 0x60100000 0 0xfe00000>;
> > >                         reg-names = "dbi", "atu", "app", "config";
> > >                         #address-cells = <3>;
> > >                         #size-cells = <2>;
> > >                         device_type = "pci";
> > >                         linux,pci-domain = <0>;
> > >                         bus-range = <0x00 0xff>;
> > >                         ranges = <0x81000000 0x0 0x00000000 0x0 0x6ff00000 0 0x00100000>,
> > >                                  <0x82000000 0x0 0x10000000 0x9 0x10000000 0 0x10000000>;
> > >                         num-lanes = <1>;
> > >                         num-viewport = <8>;
> > >                         interrupts = <GIC_SPI 310 IRQ_TYPE_LEVEL_HIGH>;
> > >                         interrupt-names = "msi";
> > >                         #interrupt-cells = <1>;
> > >                         interrupt-map-mask = <0 0 0 0x7>;
> > >                         interrupt-map = <0 0 0 1 &gic 0 0 GIC_SPI 309 IRQ_TYPE_LEVEL_HIGH>,
> > >                                         <0 0 0 2 &gic 0 0 GIC_SPI 308 IRQ_TYPE_LEVEL_HIGH>,
> > >                                         <0 0 0 3 &gic 0 0 GIC_SPI 307 IRQ_TYPE_LEVEL_HIGH>,
> > >                                         <0 0 0 4 &gic 0 0 GIC_SPI 306 IRQ_TYPE_LEVEL_HIGH>;
> > >                         fsl,max-link-speed = <3>;
> > >                         clocks = <&scmi_clk IMX95_CLK_HSIO>,
> > >                                  <&scmi_clk IMX95_CLK_HSIOPLL>,
> > >                                  <&scmi_clk IMX95_CLK_HSIOPLL_VCO>,
> > >                                  <&scmi_clk IMX95_CLK_HSIOPCIEAUX>;
> > >                         clock-names = "pcie", "pcie_bus", "pcie_phy", "pcie_aux";
> > >                         assigned-clocks =<&scmi_clk IMX95_CLK_HSIOPLL_VCO>,
> > >                                          <&scmi_clk IMX95_CLK_HSIOPLL>,
> > >                                          <&scmi_clk IMX95_CLK_HSIOPCIEAUX>;
> > >                         assigned-clock-rates = <3600000000>, <100000000>, <10000000>;
> > >                         assigned-clock-parents = <0>, <0>,
> > >                                                  <&scmi_clk IMX95_CLK_SYSPLL1_PFD1_DIV2>;
> > >                         power-domains = <&scmi_devpd IMX95_PD_HSIO_TOP>;
> > >                         /* 0x30~0x37 stream id for pci0 */
> > >                         /*
> > >                          * iommu-map = <0x000 &apps_smmu 0x30 0x1>,
> > >                          * <0x100 &apps_smmu 0x31 0x1>;
> > >                          */
> > >                         status = "disabled";
> > >                 };
> > > 
> > > pcie1: pcie-ep@4c380000 {
> > >                         compatible = "fsl,imx95-pcie-ep";
> > >                         reg = <0 0x4c380000 0 0x20000>,
> > >                               <0 0x4c3e0000 0 0x1000>,
> > >                               <0 0x4c3a0000 0 0x1000>,
> > >                               <0 0x4c3c0000 0 0x10000>,
> > >                               <0 0x4c3f0000 0 0x10000>,
> > >                               <0xa 0 1 0>;
> > >                         reg-names = "dbi", "atu", "dbi2", "app", "dma", "addr_space";
> > >                         interrupts = <GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH>;
> > >                         interrupt-names = "dma";
> > >                         fsl,max-link-speed = <3>;
> > >                         clocks = <&scmi_clk IMX95_CLK_HSIO>,
> > >                                  <&scmi_clk IMX95_CLK_HSIOPLL>,
> > >                                  <&scmi_clk IMX95_CLK_HSIOPLL_VCO>,
> > >                                  <&scmi_clk IMX95_CLK_HSIOPCIEAUX>;
> > >                         clock-names = "pcie", "pcie_bus", "pcie_phy", "pcie_aux";
> > >                         assigned-clocks =<&scmi_clk IMX95_CLK_HSIOPLL_VCO>,
> > >                                          <&scmi_clk IMX95_CLK_HSIOPLL>,
> > >                                          <&scmi_clk IMX95_CLK_HSIOPCIEAUX>;
> > >                         assigned-clock-rates = <3600000000>, <100000000>, <10000000>;
> > >                         assigned-clock-parents = <0>, <0>,
> > >                                                  <&scmi_clk IMX95_CLK_SYSPLL1_PFD1_DIV2>;
> > >                         power-domains = <&scmi_devpd IMX95_PD_HSIO_TOP>;
> > >                         status = "disabled";
> > >                 };
> > > 
> > > Frank Li (13):
> > >   PCI: imx6: Simplify clock handling by using clk_bulk*() function
> > >   PCI: imx6: Simplify phy handling by using IMX6_PCIE_FLAG_HAS_PHYDRV
> > >   PCI: imx6: Simplify reset handling by using by using
> > >     *_FLAG_HAS_*_RESET
> > >   PCI: imx6: Simplify ltssm_enable() by using ltssm_off and ltssm_mask
> > >   PCI: imx6: Simplify configure_type() by using mode_off and mode_mask
> > >   PCI: imx6: Simplify switch-case logic by involve init_phy callback
> > >   dt-bindings: imx6q-pcie: Clean up irrationality clocks check
> > >   dt-bindings: imx6q-pcie: Restruct reg and reg-name
> > >   PCI: imx6: Add iMX95 PCIe Root Complex support
> > >   PCI: imx6: Clean up get addr_space code
> > >   PCI: imx6: Add epc_features in imx6_pcie_drvdata
> > >   dt-bindings: imx6q-pcie: Add iMX95 pcie endpoint compatible string
> > >   PCI: imx6: Add iMX95 Endpoint (EP) support
> > > 
> > > Richard Zhu (1):
> > >   dt-bindings: imx6q-pcie: Add imx95 pcie compatible string
> > > 
> > >  .../bindings/pci/fsl,imx6q-pcie-common.yaml   |  17 +-
> > >  .../bindings/pci/fsl,imx6q-pcie-ep.yaml       |  46 +-
> > >  .../bindings/pci/fsl,imx6q-pcie.yaml          |  49 +-
> > >  drivers/pci/controller/dwc/pci-imx6.c         | 634 ++++++++++--------
> > >  4 files changed, 436 insertions(+), 310 deletions(-)
> > > 
> > > -- 
> > > 2.34.1
> > >
Manivannan Sadhasivam Feb. 19, 2024, 4:12 p.m. UTC | #4 
On Mon, Feb 19, 2024 at 10:11:45AM -0500, Frank Li wrote:
> On Mon, Feb 05, 2024 at 12:33:21PM -0500, Frank Li wrote:
> > first 6 patches use drvdata: flags to simplify some switch-case code.
> > Improve maintaince and easy to read code.
> > 
> 
> @Lorenzo Pieralisi:
> 
> 	Do you have chance to look other patches?
> 	Mani's apply EP side change. 

Even though the controller is for the endpoint, it is still a controller
driver. So all the patches should go through Lorenzo.

I only merge patches under drivers/pci/endpoint. Hope this clarifies.

- Mani

> 	'PCI: imx6: Add iMX95 Endpoint (EP) support' need be rebased. 
> 
> Frank
> 
> > Then add imx95 basic pci host function.
> > 
> > follow two patch do endpoint code clean up.
> > Then add imx95 basic endpont function.
> > 
> > Compared with v2, added EP function support and some fixes,  please change
> > notes at each patches.
> > 
> > Change from v9 to v10
> > - remove two patches:
> > >   dt-bindings: imx6q-pcie: Add linux,pci-domain as required for iMX8MQ
> > >   PCI: imx6: Using "linux,pci-domain" as slot ID
> > it is not good solution to fixed hardcode check to get controller id.
> > Will see better solution later.
> > 
> > dt-binding pass pcie node:
> > 
> > pcie0: pcie@4c300000 {
> >                         compatible = "fsl,imx95-pcie";
> >                         reg = <0 0x4c300000 0 0x40000>,
> >                                 <0 0x4c360000 0 0x10000>,
> >                                 <0 0x4c340000 0 0x20000>,
> >                                 <0 0x60100000 0 0xfe00000>;
> >                         reg-names = "dbi", "atu", "app", "config";
> >                         #address-cells = <3>;
> >                         #size-cells = <2>;
> >                         device_type = "pci";
> >                         linux,pci-domain = <0>;
> >                         bus-range = <0x00 0xff>;
> >                         ranges = <0x81000000 0x0 0x00000000 0x0 0x6ff00000 0 0x00100000>,
> >                                  <0x82000000 0x0 0x10000000 0x9 0x10000000 0 0x10000000>;
> >                         num-lanes = <1>;
> >                         num-viewport = <8>;
> >                         interrupts = <GIC_SPI 310 IRQ_TYPE_LEVEL_HIGH>;
> >                         interrupt-names = "msi";
> >                         #interrupt-cells = <1>;
> >                         interrupt-map-mask = <0 0 0 0x7>;
> >                         interrupt-map = <0 0 0 1 &gic 0 0 GIC_SPI 309 IRQ_TYPE_LEVEL_HIGH>,
> >                                         <0 0 0 2 &gic 0 0 GIC_SPI 308 IRQ_TYPE_LEVEL_HIGH>,
> >                                         <0 0 0 3 &gic 0 0 GIC_SPI 307 IRQ_TYPE_LEVEL_HIGH>,
> >                                         <0 0 0 4 &gic 0 0 GIC_SPI 306 IRQ_TYPE_LEVEL_HIGH>;
> >                         fsl,max-link-speed = <3>;
> >                         clocks = <&scmi_clk IMX95_CLK_HSIO>,
> >                                  <&scmi_clk IMX95_CLK_HSIOPLL>,
> >                                  <&scmi_clk IMX95_CLK_HSIOPLL_VCO>,
> >                                  <&scmi_clk IMX95_CLK_HSIOPCIEAUX>;
> >                         clock-names = "pcie", "pcie_bus", "pcie_phy", "pcie_aux";
> >                         assigned-clocks =<&scmi_clk IMX95_CLK_HSIOPLL_VCO>,
> >                                          <&scmi_clk IMX95_CLK_HSIOPLL>,
> >                                          <&scmi_clk IMX95_CLK_HSIOPCIEAUX>;
> >                         assigned-clock-rates = <3600000000>, <100000000>, <10000000>;
> >                         assigned-clock-parents = <0>, <0>,
> >                                                  <&scmi_clk IMX95_CLK_SYSPLL1_PFD1_DIV2>;
> >                         power-domains = <&scmi_devpd IMX95_PD_HSIO_TOP>;
> >                         /* 0x30~0x37 stream id for pci0 */
> >                         /*
> >                          * iommu-map = <0x000 &apps_smmu 0x30 0x1>,
> >                          * <0x100 &apps_smmu 0x31 0x1>;
> >                          */
> >                         status = "disabled";
> >                 };
> > 
> > pcie1: pcie-ep@4c380000 {
> >                         compatible = "fsl,imx95-pcie-ep";
> >                         reg = <0 0x4c380000 0 0x20000>,
> >                               <0 0x4c3e0000 0 0x1000>,
> >                               <0 0x4c3a0000 0 0x1000>,
> >                               <0 0x4c3c0000 0 0x10000>,
> >                               <0 0x4c3f0000 0 0x10000>,
> >                               <0xa 0 1 0>;
> >                         reg-names = "dbi", "atu", "dbi2", "app", "dma", "addr_space";
> >                         interrupts = <GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH>;
> >                         interrupt-names = "dma";
> >                         fsl,max-link-speed = <3>;
> >                         clocks = <&scmi_clk IMX95_CLK_HSIO>,
> >                                  <&scmi_clk IMX95_CLK_HSIOPLL>,
> >                                  <&scmi_clk IMX95_CLK_HSIOPLL_VCO>,
> >                                  <&scmi_clk IMX95_CLK_HSIOPCIEAUX>;
> >                         clock-names = "pcie", "pcie_bus", "pcie_phy", "pcie_aux";
> >                         assigned-clocks =<&scmi_clk IMX95_CLK_HSIOPLL_VCO>,
> >                                          <&scmi_clk IMX95_CLK_HSIOPLL>,
> >                                          <&scmi_clk IMX95_CLK_HSIOPCIEAUX>;
> >                         assigned-clock-rates = <3600000000>, <100000000>, <10000000>;
> >                         assigned-clock-parents = <0>, <0>,
> >                                                  <&scmi_clk IMX95_CLK_SYSPLL1_PFD1_DIV2>;
> >                         power-domains = <&scmi_devpd IMX95_PD_HSIO_TOP>;
> >                         status = "disabled";
> >                 };
> > 
> > Frank Li (13):
> >   PCI: imx6: Simplify clock handling by using clk_bulk*() function
> >   PCI: imx6: Simplify phy handling by using IMX6_PCIE_FLAG_HAS_PHYDRV
> >   PCI: imx6: Simplify reset handling by using by using
> >     *_FLAG_HAS_*_RESET
> >   PCI: imx6: Simplify ltssm_enable() by using ltssm_off and ltssm_mask
> >   PCI: imx6: Simplify configure_type() by using mode_off and mode_mask
> >   PCI: imx6: Simplify switch-case logic by involve init_phy callback
> >   dt-bindings: imx6q-pcie: Clean up irrationality clocks check
> >   dt-bindings: imx6q-pcie: Restruct reg and reg-name
> >   PCI: imx6: Add iMX95 PCIe Root Complex support
> >   PCI: imx6: Clean up get addr_space code
> >   PCI: imx6: Add epc_features in imx6_pcie_drvdata
> >   dt-bindings: imx6q-pcie: Add iMX95 pcie endpoint compatible string
> >   PCI: imx6: Add iMX95 Endpoint (EP) support
> > 
> > Richard Zhu (1):
> >   dt-bindings: imx6q-pcie: Add imx95 pcie compatible string
> > 
> >  .../bindings/pci/fsl,imx6q-pcie-common.yaml   |  17 +-
> >  .../bindings/pci/fsl,imx6q-pcie-ep.yaml       |  46 +-
> >  .../bindings/pci/fsl,imx6q-pcie.yaml          |  49 +-
> >  drivers/pci/controller/dwc/pci-imx6.c         | 634 ++++++++++--------
> >  4 files changed, 436 insertions(+), 310 deletions(-)
> > 
> > -- 
> > 2.34.1
> >
Frank Li Feb. 19, 2024, 4:18 p.m. UTC | #5 
On Mon, Feb 19, 2024 at 09:42:08PM +0530, Manivannan Sadhasivam wrote:
> On Mon, Feb 19, 2024 at 10:11:45AM -0500, Frank Li wrote:
> > On Mon, Feb 05, 2024 at 12:33:21PM -0500, Frank Li wrote:
> > > first 6 patches use drvdata: flags to simplify some switch-case code.
> > > Improve maintaince and easy to read code.
> > > 
> > 
> > @Lorenzo Pieralisi:
> > 
> > 	Do you have chance to look other patches?
> > 	Mani's apply EP side change. 
> 
> Even though the controller is for the endpoint, it is still a controller
> driver. So all the patches should go through Lorenzo.
> 
> I only merge patches under drivers/pci/endpoint. Hope this clarifies.

Sorry. It confused everyone. My means was that Mani applied Niklas Cassel's
patches, which cause my 14th patch build failure.

I asked if I need update my 14th patch or applied 1-13 only. 

Frank Li

> 
> - Mani
> 
> > 	'PCI: imx6: Add iMX95 Endpoint (EP) support' need be rebased. 
> > 
> > Frank
> > 
> > > Then add imx95 basic pci host function.
> > > 
> > > follow two patch do endpoint code clean up.
> > > Then add imx95 basic endpont function.
> > > 
> > > Compared with v2, added EP function support and some fixes,  please change
> > > notes at each patches.
> > > 
> > > Change from v9 to v10
> > > - remove two patches:
> > > >   dt-bindings: imx6q-pcie: Add linux,pci-domain as required for iMX8MQ
> > > >   PCI: imx6: Using "linux,pci-domain" as slot ID
> > > it is not good solution to fixed hardcode check to get controller id.
> > > Will see better solution later.
> > > 
> > > dt-binding pass pcie node:
> > > 
> > > pcie0: pcie@4c300000 {
> > >                         compatible = "fsl,imx95-pcie";
> > >                         reg = <0 0x4c300000 0 0x40000>,
> > >                                 <0 0x4c360000 0 0x10000>,
> > >                                 <0 0x4c340000 0 0x20000>,
> > >                                 <0 0x60100000 0 0xfe00000>;
> > >                         reg-names = "dbi", "atu", "app", "config";
> > >                         #address-cells = <3>;
> > >                         #size-cells = <2>;
> > >                         device_type = "pci";
> > >                         linux,pci-domain = <0>;
> > >                         bus-range = <0x00 0xff>;
> > >                         ranges = <0x81000000 0x0 0x00000000 0x0 0x6ff00000 0 0x00100000>,
> > >                                  <0x82000000 0x0 0x10000000 0x9 0x10000000 0 0x10000000>;
> > >                         num-lanes = <1>;
> > >                         num-viewport = <8>;
> > >                         interrupts = <GIC_SPI 310 IRQ_TYPE_LEVEL_HIGH>;
> > >                         interrupt-names = "msi";
> > >                         #interrupt-cells = <1>;
> > >                         interrupt-map-mask = <0 0 0 0x7>;
> > >                         interrupt-map = <0 0 0 1 &gic 0 0 GIC_SPI 309 IRQ_TYPE_LEVEL_HIGH>,
> > >                                         <0 0 0 2 &gic 0 0 GIC_SPI 308 IRQ_TYPE_LEVEL_HIGH>,
> > >                                         <0 0 0 3 &gic 0 0 GIC_SPI 307 IRQ_TYPE_LEVEL_HIGH>,
> > >                                         <0 0 0 4 &gic 0 0 GIC_SPI 306 IRQ_TYPE_LEVEL_HIGH>;
> > >                         fsl,max-link-speed = <3>;
> > >                         clocks = <&scmi_clk IMX95_CLK_HSIO>,
> > >                                  <&scmi_clk IMX95_CLK_HSIOPLL>,
> > >                                  <&scmi_clk IMX95_CLK_HSIOPLL_VCO>,
> > >                                  <&scmi_clk IMX95_CLK_HSIOPCIEAUX>;
> > >                         clock-names = "pcie", "pcie_bus", "pcie_phy", "pcie_aux";
> > >                         assigned-clocks =<&scmi_clk IMX95_CLK_HSIOPLL_VCO>,
> > >                                          <&scmi_clk IMX95_CLK_HSIOPLL>,
> > >                                          <&scmi_clk IMX95_CLK_HSIOPCIEAUX>;
> > >                         assigned-clock-rates = <3600000000>, <100000000>, <10000000>;
> > >                         assigned-clock-parents = <0>, <0>,
> > >                                                  <&scmi_clk IMX95_CLK_SYSPLL1_PFD1_DIV2>;
> > >                         power-domains = <&scmi_devpd IMX95_PD_HSIO_TOP>;
> > >                         /* 0x30~0x37 stream id for pci0 */
> > >                         /*
> > >                          * iommu-map = <0x000 &apps_smmu 0x30 0x1>,
> > >                          * <0x100 &apps_smmu 0x31 0x1>;
> > >                          */
> > >                         status = "disabled";
> > >                 };
> > > 
> > > pcie1: pcie-ep@4c380000 {
> > >                         compatible = "fsl,imx95-pcie-ep";
> > >                         reg = <0 0x4c380000 0 0x20000>,
> > >                               <0 0x4c3e0000 0 0x1000>,
> > >                               <0 0x4c3a0000 0 0x1000>,
> > >                               <0 0x4c3c0000 0 0x10000>,
> > >                               <0 0x4c3f0000 0 0x10000>,
> > >                               <0xa 0 1 0>;
> > >                         reg-names = "dbi", "atu", "dbi2", "app", "dma", "addr_space";
> > >                         interrupts = <GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH>;
> > >                         interrupt-names = "dma";
> > >                         fsl,max-link-speed = <3>;
> > >                         clocks = <&scmi_clk IMX95_CLK_HSIO>,
> > >                                  <&scmi_clk IMX95_CLK_HSIOPLL>,
> > >                                  <&scmi_clk IMX95_CLK_HSIOPLL_VCO>,
> > >                                  <&scmi_clk IMX95_CLK_HSIOPCIEAUX>;
> > >                         clock-names = "pcie", "pcie_bus", "pcie_phy", "pcie_aux";
> > >                         assigned-clocks =<&scmi_clk IMX95_CLK_HSIOPLL_VCO>,
> > >                                          <&scmi_clk IMX95_CLK_HSIOPLL>,
> > >                                          <&scmi_clk IMX95_CLK_HSIOPCIEAUX>;
> > >                         assigned-clock-rates = <3600000000>, <100000000>, <10000000>;
> > >                         assigned-clock-parents = <0>, <0>,
> > >                                                  <&scmi_clk IMX95_CLK_SYSPLL1_PFD1_DIV2>;
> > >                         power-domains = <&scmi_devpd IMX95_PD_HSIO_TOP>;
> > >                         status = "disabled";
> > >                 };
> > > 
> > > Frank Li (13):
> > >   PCI: imx6: Simplify clock handling by using clk_bulk*() function
> > >   PCI: imx6: Simplify phy handling by using IMX6_PCIE_FLAG_HAS_PHYDRV
> > >   PCI: imx6: Simplify reset handling by using by using
> > >     *_FLAG_HAS_*_RESET
> > >   PCI: imx6: Simplify ltssm_enable() by using ltssm_off and ltssm_mask
> > >   PCI: imx6: Simplify configure_type() by using mode_off and mode_mask
> > >   PCI: imx6: Simplify switch-case logic by involve init_phy callback
> > >   dt-bindings: imx6q-pcie: Clean up irrationality clocks check
> > >   dt-bindings: imx6q-pcie: Restruct reg and reg-name
> > >   PCI: imx6: Add iMX95 PCIe Root Complex support
> > >   PCI: imx6: Clean up get addr_space code
> > >   PCI: imx6: Add epc_features in imx6_pcie_drvdata
> > >   dt-bindings: imx6q-pcie: Add iMX95 pcie endpoint compatible string
> > >   PCI: imx6: Add iMX95 Endpoint (EP) support
> > > 
> > > Richard Zhu (1):
> > >   dt-bindings: imx6q-pcie: Add imx95 pcie compatible string
> > > 
> > >  .../bindings/pci/fsl,imx6q-pcie-common.yaml   |  17 +-
> > >  .../bindings/pci/fsl,imx6q-pcie-ep.yaml       |  46 +-
> > >  .../bindings/pci/fsl,imx6q-pcie.yaml          |  49 +-
> > >  drivers/pci/controller/dwc/pci-imx6.c         | 634 ++++++++++--------
> > >  4 files changed, 436 insertions(+), 310 deletions(-)
> > > 
> > > -- 
> > > 2.34.1
> > > 
> 
> -- 
> மணிவண்ணன் சதாசிவம்
Niklas Cassel Feb. 20, 2024, 9:51 a.m. UTC | #6 
On Mon, Feb 19, 2024 at 11:18:03AM -0500, Frank Li wrote:
> On Mon, Feb 19, 2024 at 09:42:08PM +0530, Manivannan Sadhasivam wrote:
> > On Mon, Feb 19, 2024 at 10:11:45AM -0500, Frank Li wrote:
> > > On Mon, Feb 05, 2024 at 12:33:21PM -0500, Frank Li wrote:
> > > > first 6 patches use drvdata: flags to simplify some switch-case code.
> > > > Improve maintaince and easy to read code.
> > > > 
> > > 
> > > @Lorenzo Pieralisi:
> > > 
> > > 	Do you have chance to look other patches?
> > > 	Mani's apply EP side change. 
> > 
> > Even though the controller is for the endpoint, it is still a controller
> > driver. So all the patches should go through Lorenzo.
> > 
> > I only merge patches under drivers/pci/endpoint. Hope this clarifies.
> 
> Sorry. It confused everyone. My means was that Mani applied Niklas Cassel's
> patches, which cause my 14th patch build failure.

Hello Frank,

Patch 14, which adds this:

+static const struct pci_epc_features imx95_pcie_epc_features = {
+       .msi_capable = true,
+       .bar_fixed_size[1] = SZ_64K,
+       .align = SZ_4K,
+};


Should, after rebasing on Mani's pci/endpoint branch, instead look like this:

+static const struct pci_epc_features imx95_pcie_epc_features = {
+       .msi_capable = true,
+       .bar[BAR_1] = { .type = BAR_FIXED, .fixed_size = SZ_64K, },
+       .align = SZ_4K,
+};


> 
> I asked if I need update my 14th patch or applied 1-13 only. 

I see, you want the maintainers to apply 1-13, and simply drop patch 14
instead of you sending out a rebased series.

I assume that the maintainers will be fine with your suggested approach.


Kind regards,
Niklas
Lorenzo Pieralisi Feb. 20, 2024, 10:08 a.m. UTC | #7 
On Tue, Feb 20, 2024 at 10:51:17AM +0100, Niklas Cassel wrote:
> On Mon, Feb 19, 2024 at 11:18:03AM -0500, Frank Li wrote:
> > On Mon, Feb 19, 2024 at 09:42:08PM +0530, Manivannan Sadhasivam wrote:
> > > On Mon, Feb 19, 2024 at 10:11:45AM -0500, Frank Li wrote:
> > > > On Mon, Feb 05, 2024 at 12:33:21PM -0500, Frank Li wrote:
> > > > > first 6 patches use drvdata: flags to simplify some switch-case code.
> > > > > Improve maintaince and easy to read code.
> > > > > 
> > > > 
> > > > @Lorenzo Pieralisi:
> > > > 
> > > > 	Do you have chance to look other patches?
> > > > 	Mani's apply EP side change. 
> > > 
> > > Even though the controller is for the endpoint, it is still a controller
> > > driver. So all the patches should go through Lorenzo.
> > > 
> > > I only merge patches under drivers/pci/endpoint. Hope this clarifies.
> > 
> > Sorry. It confused everyone. My means was that Mani applied Niklas Cassel's
> > patches, which cause my 14th patch build failure.
> 
> Hello Frank,
> 
> Patch 14, which adds this:
> 
> +static const struct pci_epc_features imx95_pcie_epc_features = {
> +       .msi_capable = true,
> +       .bar_fixed_size[1] = SZ_64K,
> +       .align = SZ_4K,
> +};
> 
> 
> Should, after rebasing on Mani's pci/endpoint branch, instead look like this:
> 
> +static const struct pci_epc_features imx95_pcie_epc_features = {
> +       .msi_capable = true,
> +       .bar[BAR_1] = { .type = BAR_FIXED, .fixed_size = SZ_64K, },
> +       .align = SZ_4K,
> +};
> 
> 
> > 
> > I asked if I need update my 14th patch or applied 1-13 only. 
> 
> I see, you want the maintainers to apply 1-13, and simply drop patch 14
> instead of you sending out a rebased series.
> 
> I assume that the maintainers will be fine with your suggested approach.

If patch 14 has no dependencies on 1-13 yes; if it does we need to
coordinate the merge between branches in the PCI tree.

Lorenzo
Frank Li Feb. 20, 2024, 4:21 p.m. UTC | #8 
On Tue, Feb 20, 2024 at 11:08:17AM +0100, Lorenzo Pieralisi wrote:
> On Tue, Feb 20, 2024 at 10:51:17AM +0100, Niklas Cassel wrote:
> > On Mon, Feb 19, 2024 at 11:18:03AM -0500, Frank Li wrote:
> > > On Mon, Feb 19, 2024 at 09:42:08PM +0530, Manivannan Sadhasivam wrote:
> > > > On Mon, Feb 19, 2024 at 10:11:45AM -0500, Frank Li wrote:
> > > > > On Mon, Feb 05, 2024 at 12:33:21PM -0500, Frank Li wrote:
> > > > > > first 6 patches use drvdata: flags to simplify some switch-case code.
> > > > > > Improve maintaince and easy to read code.
> > > > > > 
> > > > > 
> > > > > @Lorenzo Pieralisi:
> > > > > 
> > > > > 	Do you have chance to look other patches?
> > > > > 	Mani's apply EP side change. 
> > > > 
> > > > Even though the controller is for the endpoint, it is still a controller
> > > > driver. So all the patches should go through Lorenzo.
> > > > 
> > > > I only merge patches under drivers/pci/endpoint. Hope this clarifies.
> > > 
> > > Sorry. It confused everyone. My means was that Mani applied Niklas Cassel's
> > > patches, which cause my 14th patch build failure.
> > 
> > Hello Frank,
> > 
> > Patch 14, which adds this:
> > 
> > +static const struct pci_epc_features imx95_pcie_epc_features = {
> > +       .msi_capable = true,
> > +       .bar_fixed_size[1] = SZ_64K,
> > +       .align = SZ_4K,
> > +};
> > 
> > 
> > Should, after rebasing on Mani's pci/endpoint branch, instead look like this:
> > 
> > +static const struct pci_epc_features imx95_pcie_epc_features = {
> > +       .msi_capable = true,
> > +       .bar[BAR_1] = { .type = BAR_FIXED, .fixed_size = SZ_64K, },
> > +       .align = SZ_4K,
> > +};
> > 
> > 
> > > 
> > > I asked if I need update my 14th patch or applied 1-13 only. 
> > 
> > I see, you want the maintainers to apply 1-13, and simply drop patch 14
> > instead of you sending out a rebased series.
> > 
> > I assume that the maintainers will be fine with your suggested approach.
> 
> If patch 14 has no dependencies on 1-13 yes; if it does we need to
> coordinate the merge between branches in the PCI tree.

Keep it easy. I rebase to linux-pci/endpoint and v11 patch sent out.
https://lore.kernel.org/imx/20240220161924.3871774-1-Frank.Li@nxp.com/T/#t

Frank

> 
> Lorenzo
Frank Li Feb. 20, 2024, 9:24 p.m. UTC | #9 
On Tue, Feb 20, 2024 at 11:21:28AM -0500, Frank Li wrote:
> On Tue, Feb 20, 2024 at 11:08:17AM +0100, Lorenzo Pieralisi wrote:
> > On Tue, Feb 20, 2024 at 10:51:17AM +0100, Niklas Cassel wrote:
> > > On Mon, Feb 19, 2024 at 11:18:03AM -0500, Frank Li wrote:
> > > > On Mon, Feb 19, 2024 at 09:42:08PM +0530, Manivannan Sadhasivam wrote:
> > > > > On Mon, Feb 19, 2024 at 10:11:45AM -0500, Frank Li wrote:
> > > > > > On Mon, Feb 05, 2024 at 12:33:21PM -0500, Frank Li wrote:
> > > > > > > first 6 patches use drvdata: flags to simplify some switch-case code.
> > > > > > > Improve maintaince and easy to read code.
> > > > > > > 
> > > > > > 
> > > > > > @Lorenzo Pieralisi:
> > > > > > 
> > > > > > 	Do you have chance to look other patches?
> > > > > > 	Mani's apply EP side change. 
> > > > > 
> > > > > Even though the controller is for the endpoint, it is still a controller
> > > > > driver. So all the patches should go through Lorenzo.
> > > > > 
> > > > > I only merge patches under drivers/pci/endpoint. Hope this clarifies.
> > > > 
> > > > Sorry. It confused everyone. My means was that Mani applied Niklas Cassel's
> > > > patches, which cause my 14th patch build failure.
> > > 
> > > Hello Frank,
> > > 
> > > Patch 14, which adds this:
> > > 
> > > +static const struct pci_epc_features imx95_pcie_epc_features = {
> > > +       .msi_capable = true,
> > > +       .bar_fixed_size[1] = SZ_64K,
> > > +       .align = SZ_4K,
> > > +};
> > > 
> > > 
> > > Should, after rebasing on Mani's pci/endpoint branch, instead look like this:
> > > 
> > > +static const struct pci_epc_features imx95_pcie_epc_features = {
> > > +       .msi_capable = true,
> > > +       .bar[BAR_1] = { .type = BAR_FIXED, .fixed_size = SZ_64K, },
> > > +       .align = SZ_4K,
> > > +};
> > > 
> > > 
> > > > 
> > > > I asked if I need update my 14th patch or applied 1-13 only. 
> > > 
> > > I see, you want the maintainers to apply 1-13, and simply drop patch 14
> > > instead of you sending out a rebased series.
> > > 
> > > I assume that the maintainers will be fine with your suggested approach.
> > 
> > If patch 14 has no dependencies on 1-13 yes; if it does we need to
> > coordinate the merge between branches in the PCI tree.
> 
> Keep it easy. I rebase to linux-pci/endpoint and v11 patch sent out.
> https://lore.kernel.org/imx/20240220161924.3871774-1-Frank.Li@nxp.com/T/#t

Bjorn just merge endpoint to next. v11 will work with linux-pci/next.

Frank

> 
> Frank
> 
> > 
> > Lorenzo