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Tue, 30 Jan 2024 05:58:50 +0000 From: Changhuang Liang To: Thomas Gleixner , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Philipp Zabel Cc: Ley Foon Tan , Jack Zhu , Changhuang Liang , linux-kernel@vger.kernel.org, devicetree@vger.kernel.org Subject: [PATCH v2 0/2] Add JH8100 external interrupt controller support Date: Mon, 29 Jan 2024 21:58:41 -0800 Message-Id: <20240130055843.216342-1-changhuang.liang@starfivetech.com> X-Mailer: git-send-email 2.25.1 X-ClientProxiedBy: NT0PR01CA0006.CHNPR01.prod.partner.outlook.cn (2406:e500:c510::8) To SHXPR01MB0671.CHNPR01.prod.partner.outlook.cn (2406:e500:c311:25::10) Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: SHXPR01MB0671:EE_|SHXPR01MB0878:EE_ X-MS-Office365-Filtering-Correlation-Id: 22e9ae80-66d9-423c-78a5-08dc215887b9 X-MS-Exchange-SenderADCheck: 1 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: ET8UOhXokSdCnvkVVzUum6I0AeaqDfx1y5WhOaBulyAtU8q3Rd1LsCzWyooNQLakWI8JwYMa0pVklAYuTVolAUKCxgRlkczTbyzTWHdUufm++FjToEnTLdff+ssCVzFz2HSNs9WbBsTacswn6VP4H/1/gqfwdZAkgbO2Z2pdYhBpqpXaAetsofBSZMkqvSf0ndhEKMjHVbFbaiwtwuQ/OzdqktsE7I5aBeu87ujlv/Zzi0K570yMUUumYcqnLFzT10ZH6zDjczCyGlPKjYOcKj/DhBlpWZW6NhyXMa8oy+uKq2JFbs0Q6l6NP1qg91NVO2AYc56zTuybasvu+H0a1M46KwlWUcYtxV6tAwghZ27M0DdXk5StJvlGnYY32yc8GkRwCZFAHzAatLF1JTzVlY0O10J/iWSISP0JjBJtiIYwpYrrVBP3JS5TJgFeKdkjUNcrmgs9vwbacOxPwjhr9PUEun2EvP3p9VabagoKrHoDKxviZ7e9KTinyR0iDx6oHc+LeEu4VXcTJeTtpqlLlrlRJQxXQVAjSQ3sWYCZZ4N4h/aaKyLJzX+3ktM6DR+ilxCZLa+5v7ubSyPJHn/+2RtfKazhSKbTOghzRFBB9C8= X-Forefront-Antispam-Report: CIP:255.255.255.255;CTRY:;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:SHXPR01MB0671.CHNPR01.prod.partner.outlook.cn;PTR:;CAT:NONE;SFS:(13230031)(396003)(346002)(366004)(39830400003)(136003)(230273577357003)(230173577357003)(230922051799003)(1800799012)(64100799003)(186009)(451199024)(26005)(41300700001)(1076003)(41320700001)(36756003)(38350700005)(2616005)(508600001)(40160700002)(40180700001)(54906003)(52116002)(6666004)(966005)(38100700002)(8676002)(5660300002)(110136005)(86362001)(66556008)(66476007)(4326008)(44832011)(2906002)(66946007)(8936002);DIR:OUT;SFP:1101; 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It can be used to handle high-level input interrupt signals. It also send the output interrupt signal to RISC-V PLIC. changes since v1: - Rebased on tag v6.8-rc1. - Dropped store reset_contorl. - Replaced "of_reset_control_get_by_index" with of_reset_control_get_exclusive - Printed the error code via %pe v1: https://lore.kernel.org/all/20240111023201.6187-1-changhuang.liang@starfivetech.com/ Changhuang Liang (2): dt-bindings: interrupt-controller: Add starfive,jh8100-intc irqchip: Add StarFive external interrupt controller .../starfive,jh8100-intc.yaml | 61 ++++++ MAINTAINERS | 6 + drivers/irqchip/Kconfig | 11 ++ drivers/irqchip/Makefile | 1 + drivers/irqchip/irq-starfive-jh8100-intc.c | 180 ++++++++++++++++++ 5 files changed, 259 insertions(+) create mode 100644 Documentation/devicetree/bindings/interrupt-controller/starfive,jh8100-intc.yaml create mode 100644 drivers/irqchip/irq-starfive-jh8100-intc.c --- 2.25.1