Message ID | 20240124213640.7582-1-ansuelsmth@gmail.com |
---|---|
Headers |
Return-Path: <linux-kernel+bounces-37700-ouuuleilei=gmail.com@vger.kernel.org> Delivered-To: ouuuleilei@gmail.com Received: by 2002:a05:7300:2553:b0:103:945f:af90 with SMTP id p19csp1267717dyi; Wed, 24 Jan 2024 13:37:37 -0800 (PST) X-Google-Smtp-Source: AGHT+IHDfFokz00mbCUhCQR5ilR7pH7x0MV77EoZpJMs8VPxT5VTvIxtYr+Zl1dAnWXxg7Ypdztu X-Received: by 2002:ac8:5fd6:0:b0:42a:3298:1351 with SMTP id k22-20020ac85fd6000000b0042a32981351mr3441832qta.131.1706132256880; Wed, 24 Jan 2024 13:37:36 -0800 (PST) ARC-Seal: i=2; a=rsa-sha256; t=1706132256; cv=pass; d=google.com; s=arc-20160816; b=iVGMz/8iF1vCsXL0eUU9oloiHbujYoX67tyAQclK0pjMwjSeMFyhfNR+U7uEw+nHp3 dHslPdnXEfcIVfzR9EK+mJQqiBrLXL3meU6FDCGxT4w3OfDfVnna+VYaEZlAtOLsVy0j 5Lg1cGy0j0Awx1ALqDM8Xe/7E7/jDdSwfJuBcLLnfMyYUO9bFzOYvw/GXZVdXSmSNWbp YjtpYQjuZtUz72U4/w4+mBygYLckfXAla9BKGC83ktKcczO1lqX25i74dycqAmcxhJS5 QgacojGrjtuuBfLgo+BMRdOzyPRj5ENHmeOCjh9tUrXuRuwddDnHeG60tftDefeD1NKw mpJQ== ARC-Message-Signature: i=2; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=content-transfer-encoding:mime-version:list-unsubscribe :list-subscribe:list-id:precedence:message-id:date:subject:cc:to :from:dkim-signature; bh=fOtE6Xk1J/NKQNtTqJEIAQz1hcLUCo0Y1saDef3VZSg=; fh=CCe5LV3srAvHWzapy9l7dzrUxIw0G29Ydx3kFkGCqgE=; b=yRfu3OhAz+o7+T25P5nJlZ7Eo33ODPz+u/ws3Qqlmr16mb+Y9NBPRgjc13biOWfauJ TuLeQQb5YGEmJf0I5gNzkcuE5vZ1OiC8ictzyI3XNG3cQjeE7q3TNGzhYAgBxXO/t8MK 473lXjZK43lxgVZQw6wTB5hxFzdu3LhtSQfimnaphkyKYpsPOJxe5sm7c55ixDwulFF6 TllK8Dy4p7DPQYR2oqVPd648YTHCbskMdSRzYpXiDqd1w7F+bpkNlISz2UT3DSmCwttx pSasJyyiZ2eZBxioJBx9H8fpoZUgc/5jFGUuAquRPYHmhx5e06AuKYH/OEhBgrRlmC++ 9NxA== ARC-Authentication-Results: i=2; mx.google.com; dkim=pass header.i=@gmail.com header.s=20230601 header.b=CWvssRvX; arc=pass (i=1 spf=pass spfdomain=gmail.com dkim=pass dkdomain=gmail.com dmarc=pass fromdomain=gmail.com); spf=pass (google.com: domain of linux-kernel+bounces-37700-ouuuleilei=gmail.com@vger.kernel.org designates 2604:1380:45d1:ec00::1 as permitted sender) smtp.mailfrom="linux-kernel+bounces-37700-ouuuleilei=gmail.com@vger.kernel.org"; dmarc=pass (p=NONE sp=QUARANTINE dis=NONE) header.from=gmail.com Received: from ny.mirrors.kernel.org (ny.mirrors.kernel.org. [2604:1380:45d1:ec00::1]) by mx.google.com with ESMTPS id y16-20020a05622a121000b00429be628087si11154256qtx.520.2024.01.24.13.37.36 for <ouuuleilei@gmail.com> (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 24 Jan 2024 13:37:36 -0800 (PST) Received-SPF: pass (google.com: domain of linux-kernel+bounces-37700-ouuuleilei=gmail.com@vger.kernel.org designates 2604:1380:45d1:ec00::1 as permitted sender) client-ip=2604:1380:45d1:ec00::1; Authentication-Results: mx.google.com; dkim=pass header.i=@gmail.com header.s=20230601 header.b=CWvssRvX; arc=pass (i=1 spf=pass spfdomain=gmail.com dkim=pass dkdomain=gmail.com dmarc=pass fromdomain=gmail.com); spf=pass (google.com: domain of linux-kernel+bounces-37700-ouuuleilei=gmail.com@vger.kernel.org designates 2604:1380:45d1:ec00::1 as permitted sender) smtp.mailfrom="linux-kernel+bounces-37700-ouuuleilei=gmail.com@vger.kernel.org"; dmarc=pass (p=NONE sp=QUARANTINE dis=NONE) header.from=gmail.com Received: from smtp.subspace.kernel.org (wormhole.subspace.kernel.org [52.25.139.140]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ny.mirrors.kernel.org (Postfix) with ESMTPS id A969C1C23C10 for <ouuuleilei@gmail.com>; Wed, 24 Jan 2024 21:37:36 +0000 (UTC) Received: from localhost.localdomain (localhost.localdomain [127.0.0.1]) by smtp.subspace.kernel.org (Postfix) with ESMTP id F0093135A77; Wed, 24 Jan 2024 21:37:00 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b="CWvssRvX" Received: from mail-wm1-f47.google.com (mail-wm1-f47.google.com [209.85.128.47]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id A29CD131E26; Wed, 24 Jan 2024 21:36:56 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.128.47 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1706132218; cv=none; b=SUwl0ajC/kyKFfBeK9IRgdLvEalkdzjp6qAiDHB2bVts+pbA9qJHc/V4EGN8cCE5tJFd/19mzVi4BYvB7ILXCDxWDFAc0KEiDTAQfZkyXqXBPkG1ZRYOXmALUCxKA6dyReURkhZFgrY2dOlw15Q8Jznv9Ll9+Tp5LeiL3XiBIOk= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1706132218; c=relaxed/simple; bh=ER8YRl0Ubg2rVsBw6JLH22yHGovsalfF9HW2+d0UgUc=; h=From:To:Cc:Subject:Date:Message-ID:MIME-Version; b=mIJovH0qIxYP+W5PtWDPIWRAPqbwGPB/yn8OntUZWcjzfBGtMMsT8BsK/uQlkApgTtdLPv8vxbcTqmeh2ipua8C5KHjKpTHMQIwshJBipzoZeBRKhNN41HE8zxgwEkNLOdYxBOblEov7lOd6wAq1BBORogerkldS6Um9WxUqGeI= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=gmail.com; spf=pass smtp.mailfrom=gmail.com; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b=CWvssRvX; arc=none smtp.client-ip=209.85.128.47 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=gmail.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=gmail.com Received: by mail-wm1-f47.google.com with SMTP id 5b1f17b1804b1-40ec048e0c1so18917555e9.2; Wed, 24 Jan 2024 13:36:56 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20230601; t=1706132215; x=1706737015; darn=vger.kernel.org; h=content-transfer-encoding:mime-version:message-id:date:subject:cc :to:from:from:to:cc:subject:date:message-id:reply-to; bh=fOtE6Xk1J/NKQNtTqJEIAQz1hcLUCo0Y1saDef3VZSg=; b=CWvssRvX/nyDqfGGrqBChMAN+vJvDRowNlkfvGAfJxgyFVPtr0G2OUVAzQesDfbj/d bqBKAOujibLNEdS0aYiSoEzxCxYBk370D4Y0WKY4jPLr/3Bz1gi37qnlF0So5bN6T/FC z1IvTMZVHxNgSNrWYKkWa7wgxfDK9+91v6zTaV690QH56W5Qh6ImjtBKd9nH0GFTS+H5 9zQ8NeE+a5sHWx3CKFeQVimzKqSO9VmIxhE2ocTdk8n5II6c1QTfjyRiDZnbeJbx7jrF z8Ord+imHq4Sl94JnyBQSBbHaCwZUgjo45aAIGhsnfFfzfdJe4vf4kJ9c2wRI82j6Vt5 Jeaw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1706132215; x=1706737015; h=content-transfer-encoding:mime-version:message-id:date:subject:cc :to:from:x-gm-message-state:from:to:cc:subject:date:message-id :reply-to; bh=fOtE6Xk1J/NKQNtTqJEIAQz1hcLUCo0Y1saDef3VZSg=; b=NBUvVhnjdXHTJSGcnTJjQ4uioY9AO+FKosHcxnRxRfcBujTWJRDL1XMVoU8YG+k+5Y Rq7FsVbKu5QA7hEwzS/uuV6pSNcjDunrUXzeAf1b5EjbjGnz6jCxM5L0qlFmK1QvpPeW MIivHUjB7f8Y62/cbNNnpq+YdYFtMafWYw6TMUDiNeR8YO6R+t7WGSAc5S4lcBERCXsx E0SXN89cjRJp++2h506WEL76NuVEhBuRY64rY9CXaSirFNXiIGPw7zhdXZhm2GGbVfDx rEgp28kUrM1uLsnV5ziJLyCF+nCaZV5oLrc2fMWMtk1/T1NMcP3v8ZeBOtwRTg+ORfv1 RBHA== X-Gm-Message-State: AOJu0Yy6icuXWDhgRh2ZAU7fgwMrF/mLS+eZeacAsUcJwoGwoZ39CRY+ UC0FZuyRyUTWAFD81d8c21bk1Z7XFOnw9Uot/tAMQoHRXWkfJ96C X-Received: by 2002:a05:600c:3115:b0:40e:7852:bc85 with SMTP id g21-20020a05600c311500b0040e7852bc85mr2216775wmo.41.1706132214635; Wed, 24 Jan 2024 13:36:54 -0800 (PST) Received: from localhost.localdomain (93-34-89-13.ip49.fastwebnet.it. [93.34.89.13]) by smtp.googlemail.com with ESMTPSA id q13-20020a05600c46cd00b0040e89ade84bsm339466wmo.4.2024.01.24.13.36.53 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 24 Jan 2024 13:36:54 -0800 (PST) From: Christian Marangi <ansuelsmth@gmail.com> To: Andy Gross <agross@kernel.org>, Bjorn Andersson <andersson@kernel.org>, Konrad Dybcio <konrad.dybcio@linaro.org>, "David S. Miller" <davem@davemloft.net>, Eric Dumazet <edumazet@google.com>, Jakub Kicinski <kuba@kernel.org>, Paolo Abeni <pabeni@redhat.com>, Rob Herring <robh+dt@kernel.org>, Krzysztof Kozlowski <krzysztof.kozlowski+dt@linaro.org>, Conor Dooley <conor+dt@kernel.org>, Andrew Lunn <andrew@lunn.ch>, Heiner Kallweit <hkallweit1@gmail.com>, Russell King <linux@armlinux.org.uk>, Robert Marko <robert.marko@sartura.hr>, linux-arm-msm@vger.kernel.org, netdev@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Cc: Christian Marangi <ansuelsmth@gmail.com> Subject: [net-next PATCH 0/3] net: mdio-ipq4019: fix wrong default MDC rate Date: Wed, 24 Jan 2024 22:36:30 +0100 Message-ID: <20240124213640.7582-1-ansuelsmth@gmail.com> X-Mailer: git-send-email 2.43.0 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: <linux-kernel.vger.kernel.org> List-Subscribe: <mailto:linux-kernel+subscribe@vger.kernel.org> List-Unsubscribe: <mailto:linux-kernel+unsubscribe@vger.kernel.org> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1789009337602950300 X-GMAIL-MSGID: 1789009337602950300 |
Series |
net: mdio-ipq4019: fix wrong default MDC rate
|
|
Message
Christian Marangi
Jan. 24, 2024, 9:36 p.m. UTC
This was a long journey to arrive and discover this problem. To not waste too much char, there is a race problem with PHY and driver probe. This was observed with Aquantia PHY firmware loading. With some hacks the race problem was workarounded but an interesting thing was notice. It took more than a minute for the firmware to load via MDIO. This was strange as the same operation was done by UBoot in at max 5 second and the same data was loaded. A similar problem was observed on a mtk board that also had an Aquantia PHY where the load was very slow. It was notice that the cause was the MDIO bus running at a very low speed and the firmware was missing a property (present in mtk sdk) that set the right frequency to the MDIO bus. It was fun to find that THE VERY SAME PROBLEM is present on IPQ in a different form. The MDIO apply internally a division to the feed clock resulting in the bus running at 390KHz instead of 6.25Mhz. Searching around the web for some documentation and some include and analyzing the uboot codeflow resulted in the divider being set wrongly at /256 instead of /16 as the value was actually never set. Applying the value restore the original load time for the Aquantia PHY. This series mainly handle this by adding support for the "clock-frequency" property. Christian Marangi (3): dt-bindings: net: ipq4019-mdio: document now supported clock-frequency net: mdio: ipq4019: add support for clock-frequency property arm64: dts: qcom: ipq8074: add clock-frequency to MDIO node .../bindings/net/qcom,ipq4019-mdio.yaml | 10 +++ arch/arm64/boot/dts/qcom/ipq8074.dtsi | 2 + drivers/net/mdio/mdio-ipq4019.c | 68 +++++++++++++++++-- 3 files changed, 75 insertions(+), 5 deletions(-)
Comments
On 1/25/2024 5:36 AM, Christian Marangi wrote: > This was a long journey to arrive and discover this problem. > > To not waste too much char, there is a race problem with PHY and driver > probe. This was observed with Aquantia PHY firmware loading. > > With some hacks the race problem was workarounded but an interesting > thing was notice. It took more than a minute for the firmware to load > via MDIO. > > This was strange as the same operation was done by UBoot in at max 5 > second and the same data was loaded. > > A similar problem was observed on a mtk board that also had an > Aquantia PHY where the load was very slow. It was notice that the cause > was the MDIO bus running at a very low speed and the firmware > was missing a property (present in mtk sdk) that set the right frequency > to the MDIO bus. > > It was fun to find that THE VERY SAME PROBLEM is present on IPQ in a > different form. The MDIO apply internally a division to the feed clock > resulting in the bus running at 390KHz instead of 6.25Mhz. > > Searching around the web for some documentation and some include and > analyzing the uboot codeflow resulted in the divider being set wrongly > at /256 instead of /16 as the value was actually never set. > Applying the value restore the original load time for the Aquantia PHY. > > This series mainly handle this by adding support for the "clock-frequency" > property. > > Christian Marangi (3): > dt-bindings: net: ipq4019-mdio: document now supported clock-frequency > net: mdio: ipq4019: add support for clock-frequency property > arm64: dts: qcom: ipq8074: add clock-frequency to MDIO node > > .../bindings/net/qcom,ipq4019-mdio.yaml | 10 +++ > arch/arm64/boot/dts/qcom/ipq8074.dtsi | 2 + > drivers/net/mdio/mdio-ipq4019.c | 68 +++++++++++++++++-- > 3 files changed, 75 insertions(+), 5 deletions(-) > Hi Christian, Just a gentle reminder. The MDIO frequency config is already added by the following patch series. https://lore.kernel.org/netdev/28c8b31c-8dcb-4a19-9084-22c77a74b9a1@linaro.org/T/#m840cb8d269dca133c3ad3da3d112c63382ec2058 This MDIO patch series will be updated to just keep the MDIO frequency patch and DT document for this MDIO frequency property added. For CMN PLL config will be moved to the CMN PLL clock driver and the UNIPHY clock config will be moved the uniphy driver as suggested by Sergey's suggestions. Thanks.
On Thu, Jan 25, 2024 at 01:57:20PM +0800, Jie Luo wrote: > > > On 1/25/2024 5:36 AM, Christian Marangi wrote: > > This was a long journey to arrive and discover this problem. > > > > To not waste too much char, there is a race problem with PHY and driver > > probe. This was observed with Aquantia PHY firmware loading. > > > > With some hacks the race problem was workarounded but an interesting > > thing was notice. It took more than a minute for the firmware to load > > via MDIO. > > > > This was strange as the same operation was done by UBoot in at max 5 > > second and the same data was loaded. > > > > A similar problem was observed on a mtk board that also had an > > Aquantia PHY where the load was very slow. It was notice that the cause > > was the MDIO bus running at a very low speed and the firmware > > was missing a property (present in mtk sdk) that set the right frequency > > to the MDIO bus. > > > > It was fun to find that THE VERY SAME PROBLEM is present on IPQ in a > > different form. The MDIO apply internally a division to the feed clock > > resulting in the bus running at 390KHz instead of 6.25Mhz. > > > > Searching around the web for some documentation and some include and > > analyzing the uboot codeflow resulted in the divider being set wrongly > > at /256 instead of /16 as the value was actually never set. > > Applying the value restore the original load time for the Aquantia PHY. > > > > This series mainly handle this by adding support for the "clock-frequency" > > property. > > > > Christian Marangi (3): > > dt-bindings: net: ipq4019-mdio: document now supported clock-frequency > > net: mdio: ipq4019: add support for clock-frequency property > > arm64: dts: qcom: ipq8074: add clock-frequency to MDIO node > > > > .../bindings/net/qcom,ipq4019-mdio.yaml | 10 +++ > > arch/arm64/boot/dts/qcom/ipq8074.dtsi | 2 + > > drivers/net/mdio/mdio-ipq4019.c | 68 +++++++++++++++++-- > > 3 files changed, 75 insertions(+), 5 deletions(-) > > > > Hi Christian, > Just a gentle reminder. > Hi Jie, hope you can understand my reason. > The MDIO frequency config is already added by the following patch series. > https://lore.kernel.org/netdev/28c8b31c-8dcb-4a19-9084-22c77a74b9a1@linaro.org/T/#m840cb8d269dca133c3ad3da3d112c63382ec2058 > Wasn't aware of this, as I said in the cover letter this all comes by a problem we notice in the Aquantia firmware load that was slow as hell and we just notice the misconfiguration of the divisor. The feature in this series is really a simple one and almost ready (I already have v2 ready for the request from Andrew to follow 802.3 spec) and we really need it ASAP as we are trying to move our ipq807x targets to upstream driver and finally start using the integrated firmware loading for Aquantia PHY. Also I can see some fundamental difference between the 2 patch, mainly in how the value is applied and setting a sane divisor by default instead of using 0xff. (probably Andrew would have pointed out the same thing in some later revision to your series) Looking at the linked series I notice there are still some thing to polish and to clarify with DT and driver and I think it's only beneficial if this feature is worked separately as it's not only needed for ipq50xx but affects every user of this (ipq40xx, ipq807x, ipq60xx) and it would be a pitty to wait the entire ipq50xx series to be handled just to fix a long lasting misconfiguration on various SoC family. Hope you can understand these reasons, it's all for the sake of making this driver more mature quicker. > This MDIO patch series will be updated to just keep the MDIO frequency > patch and DT document for this MDIO frequency property added. > > For CMN PLL config will be moved to the CMN PLL clock driver and the UNIPHY > clock config will be moved the uniphy driver as suggested by > Sergey's suggestions. > > Thanks. > >
> Hi Christian, > Just a gentle reminder. > > The MDIO frequency config is already added by the following patch series. > https://lore.kernel.org/netdev/28c8b31c-8dcb-4a19-9084-22c77a74b9a1@linaro.org/T/#m840cb8d269dca133c3ad3da3d112c63382ec2058 I admit this version was posted first. However, its embedded in a patch series which is not making much progress, and i doubt will make progress any time soon. If you really want your version to be used, please split it out into a standalone patch series adding just MDIO clock-frequency support, with its binding, and nothing else. Andrew
On 1/26/2024 1:18 AM, Andrew Lunn wrote: >> Hi Christian, >> Just a gentle reminder. >> >> The MDIO frequency config is already added by the following patch series. >> https://lore.kernel.org/netdev/28c8b31c-8dcb-4a19-9084-22c77a74b9a1@linaro.org/T/#m840cb8d269dca133c3ad3da3d112c63382ec2058 > > I admit this version was posted first. However, its embedded in a > patch series which is not making much progress, and i doubt will make > progress any time soon. > > If you really want your version to be used, please split it out into a > standalone patch series adding just MDIO clock-frequency support, with > its binding, and nothing else. > > Andrew Hi Andrew, We will rework the patch series to include only MDIO frequency related function and frequency dt binding, and post the updated patch series on the Monday/Tuesday of next week. We will work with Christian to ensure he can re-use this patch as well. Thanks
On Fri, 26 Jan 2024 at 18:03, Jie Luo <quic_luoj@quicinc.com> wrote: > > > > On 1/26/2024 1:18 AM, Andrew Lunn wrote: > >> Hi Christian, > >> Just a gentle reminder. > >> > >> The MDIO frequency config is already added by the following patch series. > >> https://lore.kernel.org/netdev/28c8b31c-8dcb-4a19-9084-22c77a74b9a1@linaro.org/T/#m840cb8d269dca133c3ad3da3d112c63382ec2058 > > > > I admit this version was posted first. However, its embedded in a > > patch series which is not making much progress, and i doubt will make > > progress any time soon. > > > > If you really want your version to be used, please split it out into a > > standalone patch series adding just MDIO clock-frequency support, with > > its binding, and nothing else. > > > > Andrew > > Hi Andrew, > We will rework the patch series to include only MDIO frequency related > function and frequency dt binding, and post the updated patch series > on the Monday/Tuesday of next week. We will work with Christian to > ensure he can re-use this patch as well. Can you do the other way around: rebase your patches on top of Chritian's work?
On Fri, Jan 26, 2024 at 07:20:03PM +0200, Dmitry Baryshkov wrote: > On Fri, 26 Jan 2024 at 18:03, Jie Luo <quic_luoj@quicinc.com> wrote: > > > > > > > > On 1/26/2024 1:18 AM, Andrew Lunn wrote: > > >> Hi Christian, > > >> Just a gentle reminder. > > >> > > >> The MDIO frequency config is already added by the following patch series. > > >> https://lore.kernel.org/netdev/28c8b31c-8dcb-4a19-9084-22c77a74b9a1@linaro.org/T/#m840cb8d269dca133c3ad3da3d112c63382ec2058 > > > > > > I admit this version was posted first. However, its embedded in a > > > patch series which is not making much progress, and i doubt will make > > > progress any time soon. > > > > > > If you really want your version to be used, please split it out into a > > > standalone patch series adding just MDIO clock-frequency support, with > > > its binding, and nothing else. > > > > > > Andrew > > > > Hi Andrew, > > We will rework the patch series to include only MDIO frequency related > > function and frequency dt binding, and post the updated patch series > > on the Monday/Tuesday of next week. We will work with Christian to > > ensure he can re-use this patch as well. > > Can you do the other way around: rebase your patches on top of Chritian's work? > Would be ideal, also I have to send v2 that handle the 802.3 suggested MDC rate (ready I just need to send after this has been handled). Also I can see some problem with Lui patch where the divisor value is not reapplied after MDIO reset effectively reverting to the default value. If it's a credits problem I can totally change the from or add Co-devloped, I just need the feature since the thing is broken from a looong time on ipq40xx and ipq807x.
On 1/27/2024 1:33 AM, Christian Marangi wrote: > On Fri, Jan 26, 2024 at 07:20:03PM +0200, Dmitry Baryshkov wrote: >> On Fri, 26 Jan 2024 at 18:03, Jie Luo <quic_luoj@quicinc.com> wrote: >>> >>> >>> >>> On 1/26/2024 1:18 AM, Andrew Lunn wrote: >>>>> Hi Christian, >>>>> Just a gentle reminder. >>>>> >>>>> The MDIO frequency config is already added by the following patch series. >>>>> https://lore.kernel.org/netdev/28c8b31c-8dcb-4a19-9084-22c77a74b9a1@linaro.org/T/#m840cb8d269dca133c3ad3da3d112c63382ec2058 >>>> >>>> I admit this version was posted first. However, its embedded in a >>>> patch series which is not making much progress, and i doubt will make >>>> progress any time soon. >>>> >>>> If you really want your version to be used, please split it out into a >>>> standalone patch series adding just MDIO clock-frequency support, with >>>> its binding, and nothing else. >>>> >>>> Andrew >>> >>> Hi Andrew, >>> We will rework the patch series to include only MDIO frequency related >>> function and frequency dt binding, and post the updated patch series >>> on th/Tuesdae Mondayy of next week. We will work with Christian to >>> ensure he can re-use this patch as well. >> >> Can you do the other way around: rebase your patches on top of Chritian's work? Hi Dmitry, Sure, we can take this approach if fine by Andrew as well. >> > > Would be ideal, also I have to send v2 that handle the 802.3 suggested > MDC rate (ready I just need to send after this has been handled). > > Also I can see some problem with Lui patch where thse divior > value is not reapplied after MDIO reset effectively reverting to the > default value. Hi Christian, In my version, the divisor is programmed in every MDIO operation and hence I did not add the code to revert to configured value in reset function. But sure. we can program it once during the probe/reset and avoid doing it during read/write ops. In addition, the MDIO divisor 1, 2 and 4 are not supported by the MDIO hardware block, maybe we can remove these macros to avoid confusion, or add a comment mentioning that these are not supported. > > If it's a credits problem I can totally change the from or add > Co-devloped, I just need the feature since the thing is broken from a > looong time on ipq40xx and ipq807x. >
On Mon, Jan 29, 2024 at 09:59:03PM +0800, Jie Luo wrote: > > > On 1/27/2024 1:33 AM, Christian Marangi wrote: > > On Fri, Jan 26, 2024 at 07:20:03PM +0200, Dmitry Baryshkov wrote: > > > On Fri, 26 Jan 2024 at 18:03, Jie Luo <quic_luoj@quicinc.com> wrote: > > > > > > > > > > > > > > > > On 1/26/2024 1:18 AM, Andrew Lunn wrote: > > > > > > Hi Christian, > > > > > > Just a gentle reminder. > > > > > > > > > > > > The MDIO frequency config is already added by the following patch series. > > > > > > https://lore.kernel.org/netdev/28c8b31c-8dcb-4a19-9084-22c77a74b9a1@linaro.org/T/#m840cb8d269dca133c3ad3da3d112c63382ec2058 > > > > > > > > > > I admit this version was posted first. However, its embedded in a > > > > > patch series which is not making much progress, and i doubt will make > > > > > progress any time soon. > > > > > > > > > > If you really want your version to be used, please split it out into a > > > > > standalone patch series adding just MDIO clock-frequency support, with > > > > > its binding, and nothing else. > > > > > > > > > > Andrew > > > > > > > > Hi Andrew, > > > > We will rework the patch series to include only MDIO frequency related > > > > function and frequency dt binding, and post the updated patch series > > > > on th/Tuesdae Mondayy of next week. We will work with Christian to > > > > ensure he can re-use this patch as well. > > > > > > Can you do the other way around: rebase your patches on top of Chritian's work? > > Hi Dmitry, > Sure, we can take this approach if fine by Andrew as well. > > > > > > > > Would be ideal, also I have to send v2 that handle the 802.3 suggested > > MDC rate (ready I just need to send after this has been handled). > > > > Also I can see some problem with Lui patch where thse divior > > value is not reapplied after MDIO reset effectively reverting to the > > default value. > > Hi Christian, > In my version, the divisor is programmed in every MDIO operation and hence I > did not add the code to revert to configured value in reset function. But > sure. we can program it once during the probe/reset and avoid doing it > during read/write ops. > > In addition, the MDIO divisor 1, 2 and 4 are not supported by the MDIO > hardware block, maybe we can remove these macros to avoid confusion, or add > a comment mentioning that these are not supported. > Hi, thanks for confirming it! In v2 I already changed the logic to start looping from divisor 8 and added comments in DT and driver about not assuring correct funcionality with those divisor. > > > > If it's a credits problem I can totally change the from or add > > Co-devloped, I just need the feature since the thing is broken from a > > looong time on ipq40xx and ipq807x. > >
On Mon, Jan 29, 2024 at 03:25:09PM +0100, Christian Marangi wrote: > On Mon, Jan 29, 2024 at 09:59:03PM +0800, Jie Luo wrote: > > > > > > On 1/27/2024 1:33 AM, Christian Marangi wrote: > > > On Fri, Jan 26, 2024 at 07:20:03PM +0200, Dmitry Baryshkov wrote: > > > > On Fri, 26 Jan 2024 at 18:03, Jie Luo <quic_luoj@quicinc.com> wrote: > > > > > > > > > > > > > > > > > > > > On 1/26/2024 1:18 AM, Andrew Lunn wrote: > > > > > > > Hi Christian, > > > > > > > Just a gentle reminder. > > > > > > > > > > > > > > The MDIO frequency config is already added by the following patch series. > > > > > > > https://lore.kernel.org/netdev/28c8b31c-8dcb-4a19-9084-22c77a74b9a1@linaro.org/T/#m840cb8d269dca133c3ad3da3d112c63382ec2058 > > > > > > > > > > > > I admit this version was posted first. However, its embedded in a > > > > > > patch series which is not making much progress, and i doubt will make > > > > > > progress any time soon. > > > > > > > > > > > > If you really want your version to be used, please split it out into a > > > > > > standalone patch series adding just MDIO clock-frequency support, with > > > > > > its binding, and nothing else. > > > > > > > > > > > > Andrew > > > > > > > > > > Hi Andrew, > > > > > We will rework the patch series to include only MDIO frequency related > > > > > function and frequency dt binding, and post the updated patch series > > > > > on th/Tuesdae Mondayy of next week. We will work with Christian to > > > > > ensure he can re-use this patch as well. > > > > > > > > Can you do the other way around: rebase your patches on top of Chritian's work? > > > > Hi Dmitry, > > Sure, we can take this approach if fine by Andrew as well. > > > > > > > > > > > > Would be ideal, also I have to send v2 that handle the 802.3 suggested > > > MDC rate (ready I just need to send after this has been handled). > > > > > > Also I can see some problem with Lui patch where thse divior > > > value is not reapplied after MDIO reset effectively reverting to the > > > default value. > > > > Hi Christian, > > In my version, the divisor is programmed in every MDIO operation and hence I > > did not add the code to revert to configured value in reset function. But > > sure. we can program it once during the probe/reset and avoid doing it > > during read/write ops. > > > > In addition, the MDIO divisor 1, 2 and 4 are not supported by the MDIO > > hardware block, maybe we can remove these macros to avoid confusion, or add > > a comment mentioning that these are not supported. > > > > Hi, thanks for confirming it! In v2 I already changed the logic to start > looping from divisor 8 and added comments in DT and driver about not > assuring correct funcionality with those divisor. Hi Christian Lets go with your version. Please post V2 whenever you are ready. Jie, please spend some time reviewing to patches, make any comments you have, and if everything is O.K, you can add a Reviewed-by: Andrew