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Wed, 24 Jan 2024 20:23:10 -0800 (PST) Received: from charlie.ba.rivosinc.com ([64.71.180.162]) by smtp.gmail.com with ESMTPSA id ko9-20020a056a00460900b006dab36287bfsm14549743pfb.207.2024.01.24.20.23.08 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 24 Jan 2024 20:23:09 -0800 (PST) From: Charlie Jenkins Subject: [PATCH v10 0/2] riscv: Create and document PR_RISCV_SET_ICACHE_FLUSH_CTX prctl Date: Wed, 24 Jan 2024 20:23:07 -0800 Message-Id: <20240124-fencei-v10-0-a25971f4301d@rivosinc.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-B4-Tracking: v=1; b=H4sIACvisWUC/23QS07EMAwG4KuMsqbIdp5lxT0Qi+bFZEE7alEEG vXuuCOmU6EsbeX77fgqljSXtIiX01XMqZalTCMXCE8nEc7D+JG6ErkhCEgiou1yGkMqXe6zgWi dygMIfnyZUy7ft6S3d67PZfma5p9bcMWt+xdBdI+o2EHnUwCHGDwhvc6lTksZw3OYPsWWUukgJ eySWFLwhuTg0WNuSPmQhHKXcptpNWpH0iVvG1LdpQKE/cNVsYwqZMq+Bx1lQ+qjdLvULIcBk8Z oiai1rTnKfpeGJShEw1YpHRrSHiQ+bmtZWpfBoEoYPTSkO0qzS8dSyUHx1VQGwobsD5Iet+23m cjr+pxctP/luq6/EfVc/3ACAAA= To: Paul Walmsley , Palmer Dabbelt , Albert Ou , Jonathan Corbet , Conor Dooley , =?utf-8?b?Q2zDqW1lbnQgTMOpZ2Vy?= , Atish Patra , Randy Dunlap , Alexandre Ghiti Cc: linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org, linux-doc@vger.kernel.org, Charlie Jenkins , Atish Patra X-Mailer: b4 0.12.3 X-Developer-Signature: v=1; a=ed25519-sha256; t=1706156588; l=2933; i=charlie@rivosinc.com; s=20231120; h=from:subject:message-id; bh=Fp/Nsdcth0hMGV4QFLJyIHW6clYIcFNJ6WEMI/uUbQg=; b=SvtUbRzRCSPcDsyKUxxcadxQoBxxmIhU4504F5DxcJ1phzCTxqjQPG4L5ty+vMNgQswrEoK5x HlIebRpycAvDGysjIrrNQ3pIhmMKVTQ3CdAEmLCsQkAYHOsQyG0xTtr X-Developer-Key: i=charlie@rivosinc.com; a=ed25519; pk=t4RSWpMV1q5lf/NWIeR9z58bcje60/dbtxxmoSfBEcs= X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1789034883900182630 X-GMAIL-MSGID: 1789034883900182630 Improve the performance of icache flushing by creating a new prctl flag PR_RISCV_SET_ICACHE_FLUSH_CTX. The interface is left generic to allow for future expansions such as with the proposed J extension [1]. Documentation is also provided to explain the use case. Patch sent to add PR_RISCV_SET_ICACHE_FLUSH_CTX to man-pages [2]. [1] https://github.com/riscv/riscv-j-extension [2] https://lore.kernel.org/linux-man/20240124-fencei_prctl-v1-1-0bddafcef331@rivosinc.com Signed-off-by: Charlie Jenkins --- Changes in v10: - Fix fence.i condition to properly only flush on migration (Alex) - Fix documentation wording (Alex) - Link to v9: https://lore.kernel.org/r/20240123-fencei-v9-0-71411bfe8d71@rivosinc.com Changes in v9: - Remove prev_cpu from mm (Alex) - Link to v8: https://lore.kernel.org/r/20240116-fencei-v8-0-43a42134f021@rivosinc.com Changes in v8: - Only flush icache if migrated to different cpu (Alex) - Move flushing to switch_to to catch per-thread flushing properly - Link to v7: https://lore.kernel.org/r/20240112-fencei-v7-0-78f0614e1db0@rivosinc.com Changes in v7: - Change "per_thread" parameter to "scope" and provide constants for the parameter. - Link to v6: https://lore.kernel.org/r/20240109-fencei-v6-0-04116e51445c@rivosinc.com Changes in v6: - Fixup documentation formatting - Link to v5: https://lore.kernel.org/r/20240108-fencei-v5-0-aa1e51d7222f@rivosinc.com Changes in v5: - Minor documentation changes (Randy) - Link to v4: https://lore.kernel.org/r/20240107-fencei-v4-0-d4cf2fb905d3@rivosinc.com Changes in v4: - Add OFF flag to disallow fence.i in userspace (Atish) - Fix documentation issues (Atish) - Link to v3: https://lore.kernel.org/r/20231213-fencei-v3-0-b75158238eb7@rivosinc.com Changes in v3: - Check if value force_icache_flush set on thread, rather than in mm twice (Clément) - Link to v2: https://lore.kernel.org/r/20231130-fencei-v2-0-2cb623ab1b1f@rivosinc.com Changes in v2: - Fix kernel-doc comment (Conor) - Link to v1: https://lore.kernel.org/r/20231122-fencei-v1-0-bec0811cb212@rivosinc.com --- Charlie Jenkins (2): riscv: Include riscv_set_icache_flush_ctx prctl documentation: Document PR_RISCV_SET_ICACHE_FLUSH_CTX prctl Documentation/arch/riscv/cmodx.rst | 96 ++++++++++++++++++++++++++++++++++++++ Documentation/arch/riscv/index.rst | 1 + arch/riscv/include/asm/mmu.h | 2 + arch/riscv/include/asm/processor.h | 7 +++ arch/riscv/include/asm/switch_to.h | 13 ++++++ arch/riscv/mm/cacheflush.c | 67 ++++++++++++++++++++++++++ arch/riscv/mm/context.c | 13 ++++-- include/uapi/linux/prctl.h | 6 +++ kernel/sys.c | 6 +++ 9 files changed, 208 insertions(+), 3 deletions(-) --- base-commit: 6613476e225e090cc9aad49be7fa504e290dd33d change-id: 20231117-fencei-f9f60d784fa0