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Wed, 17 Jan 2024 17:35:20 +0000 (GMT) Received: from nalasex01a.na.qualcomm.com (nalasex01a.na.qualcomm.com [10.47.209.196]) by NALASPPMTA01.qualcomm.com (8.17.1.5/8.17.1.5) with ESMTPS id 40HHZJv5005468 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Wed, 17 Jan 2024 17:35:19 GMT Received: from hu-sibis-blr.qualcomm.com (10.80.80.8) by nalasex01a.na.qualcomm.com (10.47.209.196) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1118.40; Wed, 17 Jan 2024 09:35:15 -0800 From: Sibi Sankar To: , , , , , , CC: , , , , , , Subject: [RFC 0/7] firmware: arm_scmi: Qualcomm Vendor Protocol Date: Wed, 17 Jan 2024 23:04:51 +0530 Message-ID: <20240117173458.2312669-1-quic_sibis@quicinc.com> X-Mailer: git-send-email 2.34.1 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-ClientProxiedBy: nasanex01a.na.qualcomm.com (10.52.223.231) To nalasex01a.na.qualcomm.com (10.47.209.196) X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-GUID: dEjj_PROBZyYwT8VWUwqWpOgsz2Mdbso X-Proofpoint-ORIG-GUID: dEjj_PROBZyYwT8VWUwqWpOgsz2Mdbso X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.272,Aquarius:18.0.997,Hydra:6.0.619,FMLib:17.11.176.26 definitions=2024-01-17_10,2024-01-17_01,2023-05-22_02 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 adultscore=0 impostorscore=0 mlxscore=0 clxscore=1011 priorityscore=1501 mlxlogscore=690 bulkscore=0 lowpriorityscore=0 malwarescore=0 phishscore=0 suspectscore=0 spamscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.19.0-2311290000 definitions=main-2401170127 X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1788359943399313352 X-GMAIL-MSGID: 1788359943399313352 This patch series introduces the Qualcomm SCMI Vendor protocol and adds a client driver that interacts with the vendor protocol and passes on the required tuneables to start various features running on the SCMI controller. The series specifically enables (LLCC/DDR) dvfs on X1E80100 SoC by passing several tuneables including the IPM ratio (Instructions Per Miss), cpu frequency to memory/bus frequency tables, CPU mapping to the vendor protocol which in turn will enable the memory latency governor running on the SCMI controller. Depends on: limits changed notification v2: https://patchwork.kernel.org/project/linux-arm-msm/cover/20240117104116.2055349-1-quic_sibis@quicinc.com/ Turbo support: https://patchwork.kernel.org/project/linux-arm-msm/cover/20240117110443.2060704-1-quic_sibis@quicinc.com/ Shivnandan Kumar (2): firmware: arm_scmi: Add QCOM vendor protocol soc: qcom: Utilize qcom scmi vendor protocol for bus dvfs Sibi Sankar (5): dt-bindings: mailbox: qcom: Add CPUCP mailbox controller bindings mailbox: Add support for QTI CPUCP mailbox controller arm64: dts: qcom: x1e80100: Add cpucp mailbox and sram nodes arm64: dts: qcom: x1e80100: Enable cpufreq arm64: dts: qcom: x1e80100: Enable LLCC/DDR dvfs .../bindings/mailbox/qcom,cpucp-mbox.yaml | 51 ++ arch/arm64/boot/dts/qcom/x1e80100.dtsi | 101 ++++ drivers/firmware/arm_scmi/Kconfig | 11 + drivers/firmware/arm_scmi/Makefile | 1 + drivers/firmware/arm_scmi/qcom_scmi_vendor.c | 160 ++++++ drivers/mailbox/Kconfig | 8 + drivers/mailbox/Makefile | 2 + drivers/mailbox/qcom-cpucp-mbox.c | 265 ++++++++++ drivers/soc/qcom/Kconfig | 10 + drivers/soc/qcom/Makefile | 1 + drivers/soc/qcom/qcom_scmi_client.c | 486 ++++++++++++++++++ include/linux/qcom_scmi_vendor.h | 36 ++ 12 files changed, 1132 insertions(+) create mode 100644 Documentation/devicetree/bindings/mailbox/qcom,cpucp-mbox.yaml create mode 100644 drivers/firmware/arm_scmi/qcom_scmi_vendor.c create mode 100644 drivers/mailbox/qcom-cpucp-mbox.c create mode 100644 drivers/soc/qcom/qcom_scmi_client.c create mode 100644 include/linux/qcom_scmi_vendor.h