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Fri, 12 Jan 2024 15:56:22 -0800 (PST) Received: from charlie.ba.rivosinc.com ([64.71.180.162]) by smtp.gmail.com with ESMTPSA id jc14-20020a17090325ce00b001d3b3ac2d7bsm3725537plb.245.2024.01.12.15.56.21 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 12 Jan 2024 15:56:21 -0800 (PST) From: Charlie Jenkins Subject: [PATCH v7 0/2] riscv: Create and document PR_RISCV_SET_ICACHE_FLUSH_CTX prctl Date: Fri, 12 Jan 2024 15:56:19 -0800 Message-Id: <20240112-fencei-v7-0-78f0614e1db0@rivosinc.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-B4-Tracking: v=1; b=H4sIAKPRoWUC/23Py07DMBAF0F+pvMbIM36GFf9RsfCTekGCbGQVV fl3nIqaCGV5Rz53PDdSY8mxkpfTjZTYcs3L3IN+OhF/sfN7pDn0TJAhBwBNU5x9zDRNSbGgjUi Wkf74s8SUr/ei81vPl1y/lvJ9722wTX8rEB8VDSijLnpmALxDwNeS21Lz7J/98kG2loY7ydmQ2 CV6p5BbBw7SgeR/EoEPybedWoI0yE10+kCKhxQM2Di4iS6D8AmTm5gM/EDKvTRDyi6thSghaEQ 8+q3ay2lI1SUTAKpbIaT/J9d1/QFjEzRawQEAAA== To: Paul Walmsley , Palmer Dabbelt , Albert Ou , Jonathan Corbet , Conor Dooley , =?utf-8?b?Q2zDqW1lbnQgTMOpZ2Vy?= , Atish Patra , Randy Dunlap Cc: linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org, linux-doc@vger.kernel.org, Charlie Jenkins , Atish Patra X-Mailer: b4 0.12.3 X-Developer-Signature: v=1; a=ed25519-sha256; t=1705103781; l=2142; i=charlie@rivosinc.com; s=20231120; h=from:subject:message-id; bh=7NrtzZUolbE1vnII9PeZvgH9s80f0X/yu6SBfBeEopk=; b=HXQxAQ9NQYkhFje02cXtnO0r4RIu8BhoepGEzSabovWAoFxMm370RSGcwi/8QMIe504Z/ZWoz UGWzld43/vFAHaiwNSNwGs5jUDbS0KCsFlDVMvBVtVXbSYr2TihEDos X-Developer-Key: i=charlie@rivosinc.com; a=ed25519; pk=t4RSWpMV1q5lf/NWIeR9z58bcje60/dbtxxmoSfBEcs= X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1787930933556042683 X-GMAIL-MSGID: 1787930933556042683 Improve the performance of icache flushing by creating a new prctl flag PR_RISCV_SET_ICACHE_FLUSH_CTX. The interface is left generic to allow for future expansions such as with the proposed J extension [1]. Documentation is also provided to explain the use case. [1] https://github.com/riscv/riscv-j-extension Signed-off-by: Charlie Jenkins --- Changes in v7: - Change "per_thread" parameter to "scope" and provide constants for the parameter. - Link to v6: https://lore.kernel.org/r/20240109-fencei-v6-0-04116e51445c@rivosinc.com Changes in v6: - Fixup documentation formatting - Link to v5: https://lore.kernel.org/r/20240108-fencei-v5-0-aa1e51d7222f@rivosinc.com Changes in v5: - Minor documentation changes (Randy) - Link to v4: https://lore.kernel.org/r/20240107-fencei-v4-0-d4cf2fb905d3@rivosinc.com Changes in v4: - Add OFF flag to disallow fence.i in userspace (Atish) - Fix documentation issues (Atish) - Link to v3: https://lore.kernel.org/r/20231213-fencei-v3-0-b75158238eb7@rivosinc.com Changes in v3: - Check if value force_icache_flush set on thread, rather than in mm twice (Clément) - Link to v2: https://lore.kernel.org/r/20231130-fencei-v2-0-2cb623ab1b1f@rivosinc.com Changes in v2: - Fix kernel-doc comment (Conor) - Link to v1: https://lore.kernel.org/r/20231122-fencei-v1-0-bec0811cb212@rivosinc.com --- Charlie Jenkins (2): riscv: Include riscv_set_icache_flush_ctx prctl documentation: Document PR_RISCV_SET_ICACHE_FLUSH_CTX prctl Documentation/arch/riscv/cmodx.rst | 88 ++++++++++++++++++++++++++++++++++++++ Documentation/arch/riscv/index.rst | 1 + arch/riscv/include/asm/mmu.h | 2 + arch/riscv/include/asm/processor.h | 6 +++ arch/riscv/mm/cacheflush.c | 67 +++++++++++++++++++++++++++++ arch/riscv/mm/context.c | 8 ++-- include/uapi/linux/prctl.h | 6 +++ kernel/sys.c | 6 +++ 8 files changed, 181 insertions(+), 3 deletions(-) --- base-commit: b85ea95d086471afb4ad062012a4d73cd328fa86 change-id: 20231117-fencei-f9f60d784fa0