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Wed, 10 Jan 2024 11:21:17 GMT Received: from akronite-sh-dev02.qualcomm.com (10.80.80.8) by nalasex01c.na.qualcomm.com (10.47.97.35) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1118.40; Wed, 10 Jan 2024 03:21:12 -0800 From: Luo Jie <quic_luoj@quicinc.com> To: <andersson@kernel.org>, <konrad.dybcio@linaro.org>, <robh+dt@kernel.org>, <krzysztof.kozlowski+dt@linaro.org>, <conor+dt@kernel.org> CC: <linux-arm-msm@vger.kernel.org>, <devicetree@vger.kernel.org>, <linux-kernel@vger.kernel.org>, <netdev@vger.kernel.org>, <quic_kkumarcs@quicinc.com>, <quic_suruchia@quicinc.com>, <quic_soni@quicinc.com>, <quic_pavir@quicinc.com>, <quic_souravp@quicinc.com>, <quic_linchen@quicinc.com>, <quic_leiwei@quicinc.com> Subject: [PATCH 0/6] Add PPE device tree node for Qualcomm IPQ SoC Date: Wed, 10 Jan 2024 19:20:53 +0800 Message-ID: <20240110112059.2498-1-quic_luoj@quicinc.com> X-Mailer: git-send-email 2.42.0 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: <linux-kernel.vger.kernel.org> List-Subscribe: <mailto:linux-kernel+subscribe@vger.kernel.org> List-Unsubscribe: <mailto:linux-kernel+unsubscribe@vger.kernel.org> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Content-Type: text/plain X-ClientProxiedBy: nasanex01b.na.qualcomm.com (10.46.141.250) To nalasex01c.na.qualcomm.com (10.47.97.35) X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-GUID: r1Taov093tPbF2j_vgN0jLBhkg6Vpykn X-Proofpoint-ORIG-GUID: r1Taov093tPbF2j_vgN0jLBhkg6Vpykn X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.272,Aquarius:18.0.997,Hydra:6.0.619,FMLib:17.11.176.26 definitions=2023-12-09_02,2023-12-07_01,2023-05-22_02 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 adultscore=0 mlxscore=0 spamscore=0 bulkscore=0 clxscore=1015 impostorscore=0 malwarescore=0 lowpriorityscore=0 priorityscore=1501 phishscore=0 suspectscore=0 mlxlogscore=407 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.19.0-2311290000 definitions=main-2401100092 X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1787702265445025086 X-GMAIL-MSGID: 1787702265445025086 |
Series |
Add PPE device tree node for Qualcomm IPQ SoC
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Message
Jie Luo
Jan. 10, 2024, 11:20 a.m. UTC
The PPE(packet process engine) hardware block is supported by Qualcomm IPQ platforms, such as IPQ9574 and IPQ5332. The PPE includes the various packet processing modules such as the routing and bridging flow engines, L2 switch capability, VLAN and tunnels. Also included are integrated ethernet MAC and PCS(uniphy), which is used to connect with the external PHY devices by PCS. This patch series enables support for the following DTSI functionality for Qualcomm IPQ9574 and IPQ5332 chipsets. 1. Add PPE (Packet Processing Engine) HW support 2. Add IPQ9574 RDP433 board support, where the PPE is connected with qca8075 PHY and AQ PHY. 3. Add IPQ5332 RDP441 board support, where the PPE is connected with qca8386 and SFP PPE DTS depends on the NSSCC clock driver below, which provides the clocks for the PPE driver. https://lore.kernel.org/linux-arm-msm/20230825091234.32713-1-quic_devipriy@quicinc.com/ https://lore.kernel.org/linux-arm-msm/20231211-ipq5332-nsscc-v3-0-ad13bef9b137@quicinc.com/ Lei Wei (2): arm64: dts: qcom: ipq5332: Add RDP441 board device tree arm64: dts: qcom: ipq9574: Add RDP433 board device tree Luo Jie (4): arm64: dts: qcom: ipq9574: Add PPE device tree node arm64: dts: qcom: ipq5332: Add PPE device tree node arm64: dts: qcom: ipq5332: Add MDIO device tree arm64: dts: qcom: ipq9574: Add MDIO device tree arch/arm64/boot/dts/qcom/ipq5332-rdp441.dts | 51 ++ arch/arm64/boot/dts/qcom/ipq5332.dtsi | 414 ++++++++++- arch/arm64/boot/dts/qcom/ipq9574-rdp433.dts | 66 ++ arch/arm64/boot/dts/qcom/ipq9574.dtsi | 758 +++++++++++++++++++- 4 files changed, 1279 insertions(+), 10 deletions(-)
Comments
On 1/10/24 12:20, Luo Jie wrote: > The PPE(packet process engine) hardware block is supported by Qualcomm > IPQ platforms, such as IPQ9574 and IPQ5332. The PPE includes the various > packet processing modules such as the routing and bridging flow engines, > L2 switch capability, VLAN and tunnels. Also included are integrated > ethernet MAC and PCS(uniphy), which is used to connect with the external > PHY devices by PCS. > > This patch series enables support for the following DTSI functionality > for Qualcomm IPQ9574 and IPQ5332 chipsets. > > 1. Add PPE (Packet Processing Engine) HW support > > 2. Add IPQ9574 RDP433 board support, where the PPE is connected > with qca8075 PHY and AQ PHY. > > 3. Add IPQ5332 RDP441 board support, where the PPE is connected > with qca8386 and SFP > > PPE DTS depends on the NSSCC clock driver below, which provides the > clocks for the PPE driver. > https://lore.kernel.org/linux-arm-msm/20230825091234.32713-1-quic_devipriy@quicinc.com/ > https://lore.kernel.org/linux-arm-msm/20231211-ipq5332-nsscc-v3-0-ad13bef9b137@quicinc.com/ None of these describe (or even use) the compatible in the first patch of this series ("qcom,ipq9574-ppe"). I didn't check the subsequent ones, as I assume it's the same situtation, so this is a NAK. > Lei Wei (2): > arm64: dts: qcom: ipq5332: Add RDP441 board device tree > arm64: dts: qcom: ipq9574: Add RDP433 board device tree These two look unrelated? > > Luo Jie (4): > arm64: dts: qcom: ipq9574: Add PPE device tree node > arm64: dts: qcom: ipq5332: Add PPE device tree node > arm64: dts: qcom: ipq5332: Add MDIO device tree > arm64: dts: qcom: ipq9574: Add MDIO device tree Konrad
On 10/01/2024 12:20, Luo Jie wrote: > The PPE(packet process engine) hardware block is supported by Qualcomm > IPQ platforms, such as IPQ9574 and IPQ5332. The PPE includes the various > packet processing modules such as the routing and bridging flow engines, > L2 switch capability, VLAN and tunnels. Also included are integrated > ethernet MAC and PCS(uniphy), which is used to connect with the external > PHY devices by PCS. > > This patch series enables support for the following DTSI functionality > for Qualcomm IPQ9574 and IPQ5332 chipsets. > > 1. Add PPE (Packet Processing Engine) HW support > > 2. Add IPQ9574 RDP433 board support, where the PPE is connected > with qca8075 PHY and AQ PHY. > > 3. Add IPQ5332 RDP441 board support, where the PPE is connected > with qca8386 and SFP > > PPE DTS depends on the NSSCC clock driver below, which provides the > clocks for the PPE driver. DTS cannot depend on clock drivers. Maybe you meant that it depends on NSSCC clock controller DTS changes, which would be fine. However depending on drivers is neither necessary nor allowed. Best regards, Krzysztof
On 1/10/2024 7:32 PM, Konrad Dybcio wrote: > > > On 1/10/24 12:20, Luo Jie wrote: >> The PPE(packet process engine) hardware block is supported by Qualcomm >> IPQ platforms, such as IPQ9574 and IPQ5332. The PPE includes the various >> packet processing modules such as the routing and bridging flow engines, >> L2 switch capability, VLAN and tunnels. Also included are integrated >> ethernet MAC and PCS(uniphy), which is used to connect with the external >> PHY devices by PCS. >> >> This patch series enables support for the following DTSI functionality >> for Qualcomm IPQ9574 and IPQ5332 chipsets. >> >> 1. Add PPE (Packet Processing Engine) HW support >> >> 2. Add IPQ9574 RDP433 board support, where the PPE is connected >> with qca8075 PHY and AQ PHY. >> >> 3. Add IPQ5332 RDP441 board support, where the PPE is connected >> with qca8386 and SFP >> >> PPE DTS depends on the NSSCC clock driver below, which provides the >> clocks for the PPE driver. >> https://lore.kernel.org/linux-arm-msm/20230825091234.32713-1-quic_devipriy@quicinc.com/ >> https://lore.kernel.org/linux-arm-msm/20231211-ipq5332-nsscc-v3-0-ad13bef9b137@quicinc.com/ > > None of these describe (or even use) the compatible in the first > patch of this series ("qcom,ipq9574-ppe"). I didn't check the > subsequent ones, as I assume it's the same situtation, so this > is a NAK. The DT binding file was included in the PPE driver series, which documents the compatible string. https://lore.kernel.org/netdev/20240110142428.52026d9e@kernel.org/ I will hold off this DTSI patch series for now as per discussion in the series. When the series is resumed later, I will mention the link of PPE driver patch series in the cover letter, when updating this DTS patch series. Sorry for this confusion caused. > >> Lei Wei (2): >> arm64: dts: qcom: ipq5332: Add RDP441 board device tree >> arm64: dts: qcom: ipq9574: Add RDP433 board device tree > > These two look unrelated? These two patches are for adding the PPE port related configuration nodes (such as port speed, interface mode and MDIO address) which are board specific. RDP441 and RDP433 are two different board types. Perhaps the title of the patches are not clear enough. I will update the title to make it clear when the patch series resumes. > >> >> Luo Jie (4): >> arm64: dts: qcom: ipq9574: Add PPE device tree node >> arm64: dts: qcom: ipq5332: Add PPE device tree node >> arm64: dts: qcom: ipq5332: Add MDIO device tree >> arm64: dts: qcom: ipq9574: Add MDIO device tree > > Konrad
On 1/10/2024 8:13 PM, Krzysztof Kozlowski wrote: > On 10/01/2024 12:20, Luo Jie wrote: >> The PPE(packet process engine) hardware block is supported by Qualcomm >> IPQ platforms, such as IPQ9574 and IPQ5332. The PPE includes the various >> packet processing modules such as the routing and bridging flow engines, >> L2 switch capability, VLAN and tunnels. Also included are integrated >> ethernet MAC and PCS(uniphy), which is used to connect with the external >> PHY devices by PCS. >> >> This patch series enables support for the following DTSI functionality >> for Qualcomm IPQ9574 and IPQ5332 chipsets. >> >> 1. Add PPE (Packet Processing Engine) HW support >> >> 2. Add IPQ9574 RDP433 board support, where the PPE is connected >> with qca8075 PHY and AQ PHY. >> >> 3. Add IPQ5332 RDP441 board support, where the PPE is connected >> with qca8386 and SFP >> >> PPE DTS depends on the NSSCC clock driver below, which provides the >> clocks for the PPE driver. > > DTS cannot depend on clock drivers. Maybe you meant that it depends on > NSSCC clock controller DTS changes, which would be fine. However > depending on drivers is neither necessary nor allowed. > > Best regards, > Krzysztof > Yes, this DTSI series depends on the NSSCC clock controller DTS patches which are referred to in the cover letter. I will rectify the cover letter text when the series resumes later.