Message ID | 20240108-fencei-v5-0-aa1e51d7222f@rivosinc.com |
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Series |
riscv: Create and document PR_RISCV_SET_ICACHE_FLUSH_CTX prctl
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Message
Charlie Jenkins
Jan. 8, 2024, 6:42 p.m. UTC
Improve the performance of icache flushing by creating a new prctl flag
PR_RISCV_SET_ICACHE_FLUSH_CTX. The interface is left generic to allow
for future expansions such as with the proposed J extension [1].
Documentation is also provided to explain the use case.
[1] https://github.com/riscv/riscv-j-extension
Signed-off-by: Charlie Jenkins <charlie@rivosinc.com>
---
Changes in v5:
- Minor documentation changes (Randy)
- Link to v4: https://lore.kernel.org/r/20240107-fencei-v4-0-d4cf2fb905d3@rivosinc.com
Changes in v4:
- Add OFF flag to disallow fence.i in userspace (Atish)
- Fix documentation issues (Atish)
- Link to v3: https://lore.kernel.org/r/20231213-fencei-v3-0-b75158238eb7@rivosinc.com
Changes in v3:
- Check if value force_icache_flush set on thread, rather than in mm
twice (Clément)
- Link to v2: https://lore.kernel.org/r/20231130-fencei-v2-0-2cb623ab1b1f@rivosinc.com
Changes in v2:
- Fix kernel-doc comment (Conor)
- Link to v1: https://lore.kernel.org/r/20231122-fencei-v1-0-bec0811cb212@rivosinc.com
---
Charlie Jenkins (2):
riscv: Include riscv_set_icache_flush_ctx prctl
documentation: Document PR_RISCV_SET_ICACHE_FLUSH_CTX prctl
Documentation/arch/riscv/cmodx.rst | 88 ++++++++++++++++++++++++++++++++++++++
Documentation/arch/riscv/index.rst | 1 +
arch/riscv/include/asm/mmu.h | 2 +
arch/riscv/include/asm/processor.h | 6 +++
arch/riscv/mm/cacheflush.c | 56 ++++++++++++++++++++++++
arch/riscv/mm/context.c | 8 ++--
include/uapi/linux/prctl.h | 4 ++
kernel/sys.c | 6 +++
8 files changed, 168 insertions(+), 3 deletions(-)
---
base-commit: b85ea95d086471afb4ad062012a4d73cd328fa86
change-id: 20231117-fencei-f9f60d784fa0