Message ID | 20231227110038.55453-1-lpieralisi@kernel.org |
---|---|
Headers |
Return-Path: <linux-kernel+bounces-11973-ouuuleilei=gmail.com@vger.kernel.org> Delivered-To: ouuuleilei@gmail.com Received: by 2002:a05:7301:6f82:b0:100:9c79:88ff with SMTP id tb2csp1360759dyb; Wed, 27 Dec 2023 03:01:04 -0800 (PST) X-Google-Smtp-Source: AGHT+IEvGv9zckI5l74pGmvLhCB+Si1hGNsWJIY8PFbh9jsWK3C6I6JiQuaaUQZKrBJr1eUPn1nG X-Received: by 2002:a05:620a:2ef:b0:781:563a:a47c with SMTP id a15-20020a05620a02ef00b00781563aa47cmr2715420qko.151.1703674863741; Wed, 27 Dec 2023 03:01:03 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1703674863; cv=none; d=google.com; s=arc-20160816; b=H6blzn/MM2BTloVTPWYUe0I6ZaLHNeW0nSU1xQTyJ50FwikWwAEdO4X4ptNbLCIXq2 9m58znra87rnlZn4Qp5NSJqurog0Co2lKdmetKITqJjEPAttZKwIlYLZR/JnKi3bvSoS SlrkNzLuCyroEMlk0G/PUJiumNmWTujTErbe1bOLPTDdCNfbgNk8nis6Xm/9dUTIaqeE jA0RsGb4ni/o6Dz9LrpJI4bk2f8oUylx/TqeVVBAjN7vSKz8rExmvmRdxsEASk2jWgcU VIiM96sk7jgFWfmw9GfiRlSoVAygN+7eUuOwucw4+miU0ljUTnV1ixknYbUGXFuYgO/F oRug== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=content-transfer-encoding:mime-version:list-unsubscribe :list-subscribe:list-id:precedence:references:in-reply-to:message-id :date:subject:cc:to:from:dkim-signature; bh=vAWKPw7rsDK9FZKBNygklZ9DHrbmpuZ4Qi0Cz1Fh40k=; fh=gm6FgfR4TFCcyviu0TgjhQMRTf0nRaNEGL+saxPdenQ=; b=fjVzNtiIHfsY+0N5jydGZFSlm8EXCoOMV03l1gDAI9WmFR0YctVFPLFpvKT0KbmZy5 cfxh+zPJ6VxeKozSpjfFxwjRM2ow0x22OKxuzWY9w+JXThFEqcIMXOJZ/W4p3lCtNOuw uCmAxyPArGCoAJcYmGrOhdV6D8V7NaD9Bo78OjTYbk9nUOgh2ZmQPz+UU9ReCLRBcne0 8qtqbDEVnQ+GvMcLzjwLbDR3ZlXEYG/NyO92XRVxOAM2HxVKc2qrryDWA2GIKl3Zgbns 1XdLlD9yPyJzcOdF+s8PHIjF8qCWQfZXCZ8z9m5Ji+19xzCcUhHxOjnQAOF3oPKCiPxD v61w== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@kernel.org header.s=k20201202 header.b=bzdLFPbw; spf=pass (google.com: domain of linux-kernel+bounces-11973-ouuuleilei=gmail.com@vger.kernel.org designates 147.75.199.223 as permitted sender) smtp.mailfrom="linux-kernel+bounces-11973-ouuuleilei=gmail.com@vger.kernel.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=kernel.org Received: from ny.mirrors.kernel.org (ny.mirrors.kernel.org. [147.75.199.223]) by mx.google.com with ESMTPS id i14-20020a05620a248e00b0078137b394e3si9713429qkn.641.2023.12.27.03.01.03 for <ouuuleilei@gmail.com> (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 27 Dec 2023 03:01:03 -0800 (PST) Received-SPF: pass (google.com: domain of linux-kernel+bounces-11973-ouuuleilei=gmail.com@vger.kernel.org designates 147.75.199.223 as permitted sender) client-ip=147.75.199.223; Authentication-Results: mx.google.com; dkim=pass header.i=@kernel.org header.s=k20201202 header.b=bzdLFPbw; spf=pass (google.com: domain of linux-kernel+bounces-11973-ouuuleilei=gmail.com@vger.kernel.org designates 147.75.199.223 as permitted sender) smtp.mailfrom="linux-kernel+bounces-11973-ouuuleilei=gmail.com@vger.kernel.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=kernel.org Received: from smtp.subspace.kernel.org (wormhole.subspace.kernel.org [52.25.139.140]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ny.mirrors.kernel.org (Postfix) with ESMTPS id 7B3A51C21853 for <ouuuleilei@gmail.com>; Wed, 27 Dec 2023 11:01:03 +0000 (UTC) Received: from localhost.localdomain (localhost.localdomain [127.0.0.1]) by smtp.subspace.kernel.org (Postfix) with ESMTP id BA89F446AD; Wed, 27 Dec 2023 11:00:49 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="bzdLFPbw" X-Original-To: linux-kernel@vger.kernel.org Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 22CD44436F; Wed, 27 Dec 2023 11:00:45 +0000 (UTC) Received: by smtp.kernel.org (Postfix) with ESMTPSA id 662A6C433C8; Wed, 27 Dec 2023 11:00:42 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1703674845; bh=qIZiNp07P2dP+2YD1/RkaqTfi12jp8LFaMdjyfCAX6s=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=bzdLFPbwo7Z2ego4pEMqr1JcVoKZSmL2SrqX+3zdXSwRH1u0hXNiAvswuWVVL/S7t hIHU5QB6qFEMlVGoggvmSeXKkgb45SQg12B+02JZLbqws1OWr0OsgxGV72Ym+18f13 ndowEg2ethRTsQiN2+WsTChAABkL2fEogfJ5Ni54iqwUj8PaAtIx3zcUujLgvGUyLM ZbncNBWJP80aG7kPZph97WxVLXBJtC1UE/fvDn+mV5cyv31oqORnML9//v+sAfyqx6 R0B+mXdLYDxZ7Us9umIPRR35EaqYadBSt9WjiIKliRNqBTrNN3FUu6ZY5W88MbyOWD 86yhr3w8q+Jdg== From: Lorenzo Pieralisi <lpieralisi@kernel.org> To: linux-kernel@vger.kernel.org Cc: Lorenzo Pieralisi <lpieralisi@kernel.org>, linux-arm-kernel@lists.infradead.org, linux-acpi@vger.kernel.org, acpica-devel@lists.linux.dev, Mark Rutland <mark.rutland@arm.com>, Robin Murphy <robin.murphy@arm.com>, "Rafael J. Wysocki" <rafael@kernel.org>, Fang Xiang <fangxiang3@xiaomi.com>, Marc Zyngier <maz@kernel.org>, Robert Moore <robert.moore@intel.com> Subject: [PATCH v4 0/3] irqchip/gic-v3: Enable non-coherent GIC designs probing Date: Wed, 27 Dec 2023 12:00:35 +0100 Message-Id: <20231227110038.55453-1-lpieralisi@kernel.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230905104721.52199-1-lpieralisi@kernel.org> References: <20230905104721.52199-1-lpieralisi@kernel.org> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: <linux-kernel.vger.kernel.org> List-Subscribe: <mailto:linux-kernel+subscribe@vger.kernel.org> List-Unsubscribe: <mailto:linux-kernel+unsubscribe@vger.kernel.org> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1777700103747699612 X-GMAIL-MSGID: 1786432573922681963 |
Series |
irqchip/gic-v3: Enable non-coherent GIC designs probing
|
|
Message
Lorenzo Pieralisi
Dec. 27, 2023, 11 a.m. UTC
This series is v4 of previous series: v3: https://lore.kernel.org/all/20231006125929.48591-1-lpieralisi@kernel.org v2: https://lore.kernel.org/all/20230906094139.16032-1-lpieralisi@kernel.org v1: https://lore.kernel.org/all/20230905104721.52199-1-lpieralisi@kernel.org v3 -> v4: - Dropped patches [1-3], already merged - Added Linuxized ACPICA changes accepted upstream - Rebased against v6.7-rc3 v2 -> v3: - Added ACPICA temporary changes and ACPI changes to implement ECR https://bugzilla.tianocore.org/show_bug.cgi?id=4557 - ACPI changes are for testing purposes - subject to ECR code first approval v1 -> v2: - Updated DT bindings as per feedback - Updated patch[2] to use GIC quirks infrastructure Original cover letter --- The GICv3 architecture specifications provide a means for the system programmer to set the shareability and cacheability attributes the GIC components (redistributors and ITSes) use to drive memory transactions. Albeit the architecture give control over shareability/cacheability memory transactions attributes (and barriers), it is allowed to connect the GIC interconnect ports to non-coherent memory ports on the interconnect, basically tying off shareability/cacheability "wires" and de-facto making the redistributors and ITSes non-coherent memory observers. This series aims at starting a discussion over a possible solution to this problem, by adding to the GIC device tree bindings the standard dma-noncoherent property. The GIC driver uses the property to force the redistributors and ITSes shareability attributes to non-shareable, which consequently forces the driver to use CMOs on GIC memory tables. On ARM DT DMA is default non-coherent, so the GIC driver can't rely on the generic DT dma-coherent/non-coherent property management layer (of_dma_is_coherent()) which would default all GIC designs in the field as non-coherent; it has to rely on ad-hoc dma-noncoherent property handling. When a consistent approach is agreed upon for DT an equivalent binding will be put forward for ACPI based systems. Lorenzo Pieralisi (3): ACPICA: MADT: Add GICC online capable bit handling ACPICA: MADT: Add new MADT GICC/GICR/ITS non-coherent flags handling irqchip/gic-v3: Enable non-coherent redistributors/ITSes ACPI probing drivers/acpi/processor_core.c | 21 +++++++++++++++++++++ drivers/irqchip/irq-gic-common.h | 8 ++++++++ drivers/irqchip/irq-gic-v3-its.c | 4 ++++ drivers/irqchip/irq-gic-v3.c | 9 +++++++++ include/acpi/actbl2.h | 12 ++++++++++-- include/linux/acpi.h | 3 +++ 6 files changed, 55 insertions(+), 2 deletions(-)
Comments
On Wed, Dec 27, 2023 at 12:00 PM Lorenzo Pieralisi <lpieralisi@kernel.org> wrote: > > This series is v4 of previous series: > > v3: https://lore.kernel.org/all/20231006125929.48591-1-lpieralisi@kernel.org > v2: https://lore.kernel.org/all/20230906094139.16032-1-lpieralisi@kernel.org > v1: https://lore.kernel.org/all/20230905104721.52199-1-lpieralisi@kernel.org > > v3 -> v4: > - Dropped patches [1-3], already merged > - Added Linuxized ACPICA changes accepted upstream > - Rebased against v6.7-rc3 > > v2 -> v3: > - Added ACPICA temporary changes and ACPI changes to implement > ECR https://bugzilla.tianocore.org/show_bug.cgi?id=4557 > - ACPI changes are for testing purposes - subject to ECR code > first approval > > v1 -> v2: > - Updated DT bindings as per feedback > - Updated patch[2] to use GIC quirks infrastructure > > Original cover letter > --- > The GICv3 architecture specifications provide a means for the > system programmer to set the shareability and cacheability > attributes the GIC components (redistributors and ITSes) use > to drive memory transactions. > > Albeit the architecture give control over shareability/cacheability > memory transactions attributes (and barriers), it is allowed to > connect the GIC interconnect ports to non-coherent memory ports > on the interconnect, basically tying off shareability/cacheability > "wires" and de-facto making the redistributors and ITSes non-coherent > memory observers. > > This series aims at starting a discussion over a possible solution > to this problem, by adding to the GIC device tree bindings the > standard dma-noncoherent property. The GIC driver uses the property > to force the redistributors and ITSes shareability attributes to > non-shareable, which consequently forces the driver to use CMOs > on GIC memory tables. > > On ARM DT DMA is default non-coherent, so the GIC driver can't rely > on the generic DT dma-coherent/non-coherent property management layer > (of_dma_is_coherent()) which would default all GIC designs in the field > as non-coherent; it has to rely on ad-hoc dma-noncoherent property handling. > > When a consistent approach is agreed upon for DT an equivalent binding will > be put forward for ACPI based systems. > > Lorenzo Pieralisi (3): > ACPICA: MADT: Add GICC online capable bit handling > ACPICA: MADT: Add new MADT GICC/GICR/ITS non-coherent flags handling > irqchip/gic-v3: Enable non-coherent redistributors/ITSes ACPI probing > > drivers/acpi/processor_core.c | 21 +++++++++++++++++++++ > drivers/irqchip/irq-gic-common.h | 8 ++++++++ > drivers/irqchip/irq-gic-v3-its.c | 4 ++++ > drivers/irqchip/irq-gic-v3.c | 9 +++++++++ > include/acpi/actbl2.h | 12 ++++++++++-- > include/linux/acpi.h | 3 +++ > 6 files changed, 55 insertions(+), 2 deletions(-) > > -- I can apply the first 2 patches, but I would need an ACK for the 3rd one. Alternatively, feel free to add Acked-by: Rafael J. Wysocki <rafael.j.wysocki@intel.com> to the first 2 patches and route them via ARM64. Thanks!
On Wed, 03 Jan 2024 13:43:16 +0000, "Rafael J. Wysocki" <rafael@kernel.org> wrote: > > On Wed, Dec 27, 2023 at 12:00 PM Lorenzo Pieralisi > <lpieralisi@kernel.org> wrote: > > > > This series is v4 of previous series: > > > > v3: https://lore.kernel.org/all/20231006125929.48591-1-lpieralisi@kernel.org > > v2: https://lore.kernel.org/all/20230906094139.16032-1-lpieralisi@kernel.org > > v1: https://lore.kernel.org/all/20230905104721.52199-1-lpieralisi@kernel.org > > > > v3 -> v4: > > - Dropped patches [1-3], already merged > > - Added Linuxized ACPICA changes accepted upstream > > - Rebased against v6.7-rc3 > > > > v2 -> v3: > > - Added ACPICA temporary changes and ACPI changes to implement > > ECR https://bugzilla.tianocore.org/show_bug.cgi?id=4557 > > - ACPI changes are for testing purposes - subject to ECR code > > first approval > > > > v1 -> v2: > > - Updated DT bindings as per feedback > > - Updated patch[2] to use GIC quirks infrastructure > > > > Original cover letter > > --- > > The GICv3 architecture specifications provide a means for the > > system programmer to set the shareability and cacheability > > attributes the GIC components (redistributors and ITSes) use > > to drive memory transactions. > > > > Albeit the architecture give control over shareability/cacheability > > memory transactions attributes (and barriers), it is allowed to > > connect the GIC interconnect ports to non-coherent memory ports > > on the interconnect, basically tying off shareability/cacheability > > "wires" and de-facto making the redistributors and ITSes non-coherent > > memory observers. > > > > This series aims at starting a discussion over a possible solution > > to this problem, by adding to the GIC device tree bindings the > > standard dma-noncoherent property. The GIC driver uses the property > > to force the redistributors and ITSes shareability attributes to > > non-shareable, which consequently forces the driver to use CMOs > > on GIC memory tables. > > > > On ARM DT DMA is default non-coherent, so the GIC driver can't rely > > on the generic DT dma-coherent/non-coherent property management layer > > (of_dma_is_coherent()) which would default all GIC designs in the field > > as non-coherent; it has to rely on ad-hoc dma-noncoherent property handling. > > > > When a consistent approach is agreed upon for DT an equivalent binding will > > be put forward for ACPI based systems. > > > > Lorenzo Pieralisi (3): > > ACPICA: MADT: Add GICC online capable bit handling > > ACPICA: MADT: Add new MADT GICC/GICR/ITS non-coherent flags handling > > irqchip/gic-v3: Enable non-coherent redistributors/ITSes ACPI probing > > > > drivers/acpi/processor_core.c | 21 +++++++++++++++++++++ > > drivers/irqchip/irq-gic-common.h | 8 ++++++++ > > drivers/irqchip/irq-gic-v3-its.c | 4 ++++ > > drivers/irqchip/irq-gic-v3.c | 9 +++++++++ > > include/acpi/actbl2.h | 12 ++++++++++-- > > include/linux/acpi.h | 3 +++ > > 6 files changed, 55 insertions(+), 2 deletions(-) > > > > -- > > I can apply the first 2 patches, but I would need an ACK for the 3rd one. > > Alternatively, feel free to add > > Acked-by: Rafael J. Wysocki <rafael.j.wysocki@intel.com> > > to the first 2 patches and route them via ARM64. Thanks for that. I have some comments on the third patch, which I'd like to see addressed beforehand. This is probably all 6.9 material anyway (nobody is affected by this so far). M.
On Thu, Jan 04, 2024 at 11:34:48AM +0000, Marc Zyngier wrote: > On Wed, 03 Jan 2024 13:43:16 +0000, > "Rafael J. Wysocki" <rafael@kernel.org> wrote: > > > > On Wed, Dec 27, 2023 at 12:00 PM Lorenzo Pieralisi > > <lpieralisi@kernel.org> wrote: > > > > > > This series is v4 of previous series: > > > > > > v3: https://lore.kernel.org/all/20231006125929.48591-1-lpieralisi@kernel.org > > > v2: https://lore.kernel.org/all/20230906094139.16032-1-lpieralisi@kernel.org > > > v1: https://lore.kernel.org/all/20230905104721.52199-1-lpieralisi@kernel.org > > > > > > v3 -> v4: > > > - Dropped patches [1-3], already merged > > > - Added Linuxized ACPICA changes accepted upstream > > > - Rebased against v6.7-rc3 > > > > > > v2 -> v3: > > > - Added ACPICA temporary changes and ACPI changes to implement > > > ECR https://bugzilla.tianocore.org/show_bug.cgi?id=4557 > > > - ACPI changes are for testing purposes - subject to ECR code > > > first approval > > > > > > v1 -> v2: > > > - Updated DT bindings as per feedback > > > - Updated patch[2] to use GIC quirks infrastructure > > > > > > Original cover letter > > > --- > > > The GICv3 architecture specifications provide a means for the > > > system programmer to set the shareability and cacheability > > > attributes the GIC components (redistributors and ITSes) use > > > to drive memory transactions. > > > > > > Albeit the architecture give control over shareability/cacheability > > > memory transactions attributes (and barriers), it is allowed to > > > connect the GIC interconnect ports to non-coherent memory ports > > > on the interconnect, basically tying off shareability/cacheability > > > "wires" and de-facto making the redistributors and ITSes non-coherent > > > memory observers. > > > > > > This series aims at starting a discussion over a possible solution > > > to this problem, by adding to the GIC device tree bindings the > > > standard dma-noncoherent property. The GIC driver uses the property > > > to force the redistributors and ITSes shareability attributes to > > > non-shareable, which consequently forces the driver to use CMOs > > > on GIC memory tables. > > > > > > On ARM DT DMA is default non-coherent, so the GIC driver can't rely > > > on the generic DT dma-coherent/non-coherent property management layer > > > (of_dma_is_coherent()) which would default all GIC designs in the field > > > as non-coherent; it has to rely on ad-hoc dma-noncoherent property handling. > > > > > > When a consistent approach is agreed upon for DT an equivalent binding will > > > be put forward for ACPI based systems. > > > > > > Lorenzo Pieralisi (3): > > > ACPICA: MADT: Add GICC online capable bit handling > > > ACPICA: MADT: Add new MADT GICC/GICR/ITS non-coherent flags handling > > > irqchip/gic-v3: Enable non-coherent redistributors/ITSes ACPI probing > > > > > > drivers/acpi/processor_core.c | 21 +++++++++++++++++++++ > > > drivers/irqchip/irq-gic-common.h | 8 ++++++++ > > > drivers/irqchip/irq-gic-v3-its.c | 4 ++++ > > > drivers/irqchip/irq-gic-v3.c | 9 +++++++++ > > > include/acpi/actbl2.h | 12 ++++++++++-- > > > include/linux/acpi.h | 3 +++ > > > 6 files changed, 55 insertions(+), 2 deletions(-) > > > > > > -- > > > > I can apply the first 2 patches, but I would need an ACK for the 3rd one. > > > > Alternatively, feel free to add > > > > Acked-by: Rafael J. Wysocki <rafael.j.wysocki@intel.com> > > > > to the first 2 patches and route them via ARM64. > > Thanks for that. I have some comments on the third patch, which I'd > like to see addressed beforehand. This is probably all 6.9 material > anyway (nobody is affected by this so far). From a purely selfish point of view, it would be useful to have the first patch merged merely to reduce the burden of patches for vcpu hotplug.
On Thu, Jan 4, 2024 at 1:04 PM Russell King (Oracle) <linux@armlinux.org.uk> wrote: > > On Thu, Jan 04, 2024 at 11:34:48AM +0000, Marc Zyngier wrote: > > On Wed, 03 Jan 2024 13:43:16 +0000, > > "Rafael J. Wysocki" <rafael@kernel.org> wrote: > > > > > > On Wed, Dec 27, 2023 at 12:00 PM Lorenzo Pieralisi > > > <lpieralisi@kernel.org> wrote: > > > > > > > > This series is v4 of previous series: > > > > > > > > v3: https://lore.kernel.org/all/20231006125929.48591-1-lpieralisi@kernel.org > > > > v2: https://lore.kernel.org/all/20230906094139.16032-1-lpieralisi@kernel.org > > > > v1: https://lore.kernel.org/all/20230905104721.52199-1-lpieralisi@kernel.org > > > > > > > > v3 -> v4: > > > > - Dropped patches [1-3], already merged > > > > - Added Linuxized ACPICA changes accepted upstream > > > > - Rebased against v6.7-rc3 > > > > > > > > v2 -> v3: > > > > - Added ACPICA temporary changes and ACPI changes to implement > > > > ECR https://bugzilla.tianocore.org/show_bug.cgi?id=4557 > > > > - ACPI changes are for testing purposes - subject to ECR code > > > > first approval > > > > > > > > v1 -> v2: > > > > - Updated DT bindings as per feedback > > > > - Updated patch[2] to use GIC quirks infrastructure > > > > > > > > Original cover letter > > > > --- > > > > The GICv3 architecture specifications provide a means for the > > > > system programmer to set the shareability and cacheability > > > > attributes the GIC components (redistributors and ITSes) use > > > > to drive memory transactions. > > > > > > > > Albeit the architecture give control over shareability/cacheability > > > > memory transactions attributes (and barriers), it is allowed to > > > > connect the GIC interconnect ports to non-coherent memory ports > > > > on the interconnect, basically tying off shareability/cacheability > > > > "wires" and de-facto making the redistributors and ITSes non-coherent > > > > memory observers. > > > > > > > > This series aims at starting a discussion over a possible solution > > > > to this problem, by adding to the GIC device tree bindings the > > > > standard dma-noncoherent property. The GIC driver uses the property > > > > to force the redistributors and ITSes shareability attributes to > > > > non-shareable, which consequently forces the driver to use CMOs > > > > on GIC memory tables. > > > > > > > > On ARM DT DMA is default non-coherent, so the GIC driver can't rely > > > > on the generic DT dma-coherent/non-coherent property management layer > > > > (of_dma_is_coherent()) which would default all GIC designs in the field > > > > as non-coherent; it has to rely on ad-hoc dma-noncoherent property handling. > > > > > > > > When a consistent approach is agreed upon for DT an equivalent binding will > > > > be put forward for ACPI based systems. > > > > > > > > Lorenzo Pieralisi (3): > > > > ACPICA: MADT: Add GICC online capable bit handling > > > > ACPICA: MADT: Add new MADT GICC/GICR/ITS non-coherent flags handling > > > > irqchip/gic-v3: Enable non-coherent redistributors/ITSes ACPI probing > > > > > > > > drivers/acpi/processor_core.c | 21 +++++++++++++++++++++ > > > > drivers/irqchip/irq-gic-common.h | 8 ++++++++ > > > > drivers/irqchip/irq-gic-v3-its.c | 4 ++++ > > > > drivers/irqchip/irq-gic-v3.c | 9 +++++++++ > > > > include/acpi/actbl2.h | 12 ++++++++++-- > > > > include/linux/acpi.h | 3 +++ > > > > 6 files changed, 55 insertions(+), 2 deletions(-) > > > > > > > > -- > > > > > > I can apply the first 2 patches, but I would need an ACK for the 3rd one. > > > > > > Alternatively, feel free to add > > > > > > Acked-by: Rafael J. Wysocki <rafael.j.wysocki@intel.com> > > > > > > to the first 2 patches and route them via ARM64. > > > > Thanks for that. I have some comments on the third patch, which I'd > > like to see addressed beforehand. This is probably all 6.9 material > > anyway (nobody is affected by this so far). > > From a purely selfish point of view, it would be useful to have the > first patch merged merely to reduce the burden of patches for vcpu > hotplug. OK, since there will be at least one more iteration of patch [3/3] AFAICS, I'll queue up patches [1-2/3] for 6.8 (next week, though).
On Thu, Jan 04, 2024 at 02:21:44PM +0100, Rafael J. Wysocki wrote: > On Thu, Jan 4, 2024 at 1:04 PM Russell King (Oracle) > <linux@armlinux.org.uk> wrote: > > > > On Thu, Jan 04, 2024 at 11:34:48AM +0000, Marc Zyngier wrote: > > > On Wed, 03 Jan 2024 13:43:16 +0000, > > > "Rafael J. Wysocki" <rafael@kernel.org> wrote: > > > > > > > > On Wed, Dec 27, 2023 at 12:00 PM Lorenzo Pieralisi > > > > <lpieralisi@kernel.org> wrote: > > > > > > > > > > This series is v4 of previous series: > > > > > > > > > > v3: https://lore.kernel.org/all/20231006125929.48591-1-lpieralisi@kernel.org > > > > > v2: https://lore.kernel.org/all/20230906094139.16032-1-lpieralisi@kernel.org > > > > > v1: https://lore.kernel.org/all/20230905104721.52199-1-lpieralisi@kernel.org > > > > > > > > > > v3 -> v4: > > > > > - Dropped patches [1-3], already merged > > > > > - Added Linuxized ACPICA changes accepted upstream > > > > > - Rebased against v6.7-rc3 > > > > > > > > > > v2 -> v3: > > > > > - Added ACPICA temporary changes and ACPI changes to implement > > > > > ECR https://bugzilla.tianocore.org/show_bug.cgi?id=4557 > > > > > - ACPI changes are for testing purposes - subject to ECR code > > > > > first approval > > > > > > > > > > v1 -> v2: > > > > > - Updated DT bindings as per feedback > > > > > - Updated patch[2] to use GIC quirks infrastructure > > > > > > > > > > Original cover letter > > > > > --- > > > > > The GICv3 architecture specifications provide a means for the > > > > > system programmer to set the shareability and cacheability > > > > > attributes the GIC components (redistributors and ITSes) use > > > > > to drive memory transactions. > > > > > > > > > > Albeit the architecture give control over shareability/cacheability > > > > > memory transactions attributes (and barriers), it is allowed to > > > > > connect the GIC interconnect ports to non-coherent memory ports > > > > > on the interconnect, basically tying off shareability/cacheability > > > > > "wires" and de-facto making the redistributors and ITSes non-coherent > > > > > memory observers. > > > > > > > > > > This series aims at starting a discussion over a possible solution > > > > > to this problem, by adding to the GIC device tree bindings the > > > > > standard dma-noncoherent property. The GIC driver uses the property > > > > > to force the redistributors and ITSes shareability attributes to > > > > > non-shareable, which consequently forces the driver to use CMOs > > > > > on GIC memory tables. > > > > > > > > > > On ARM DT DMA is default non-coherent, so the GIC driver can't rely > > > > > on the generic DT dma-coherent/non-coherent property management layer > > > > > (of_dma_is_coherent()) which would default all GIC designs in the field > > > > > as non-coherent; it has to rely on ad-hoc dma-noncoherent property handling. > > > > > > > > > > When a consistent approach is agreed upon for DT an equivalent binding will > > > > > be put forward for ACPI based systems. > > > > > > > > > > Lorenzo Pieralisi (3): > > > > > ACPICA: MADT: Add GICC online capable bit handling > > > > > ACPICA: MADT: Add new MADT GICC/GICR/ITS non-coherent flags handling > > > > > irqchip/gic-v3: Enable non-coherent redistributors/ITSes ACPI probing > > > > > > > > > > drivers/acpi/processor_core.c | 21 +++++++++++++++++++++ > > > > > drivers/irqchip/irq-gic-common.h | 8 ++++++++ > > > > > drivers/irqchip/irq-gic-v3-its.c | 4 ++++ > > > > > drivers/irqchip/irq-gic-v3.c | 9 +++++++++ > > > > > include/acpi/actbl2.h | 12 ++++++++++-- > > > > > include/linux/acpi.h | 3 +++ > > > > > 6 files changed, 55 insertions(+), 2 deletions(-) > > > > > > > > > > -- > > > > > > > > I can apply the first 2 patches, but I would need an ACK for the 3rd one. > > > > > > > > Alternatively, feel free to add > > > > > > > > Acked-by: Rafael J. Wysocki <rafael.j.wysocki@intel.com> > > > > > > > > to the first 2 patches and route them via ARM64. > > > > > > Thanks for that. I have some comments on the third patch, which I'd > > > like to see addressed beforehand. This is probably all 6.9 material > > > anyway (nobody is affected by this so far). > > > > From a purely selfish point of view, it would be useful to have the > > first patch merged merely to reduce the burden of patches for vcpu > > hotplug. > > OK, since there will be at least one more iteration of patch [3/3] > AFAICS, I'll queue up patches [1-2/3] for 6.8 (next week, though). Thanks!
On Thu, Jan 04, 2024 at 02:21:44PM +0100, Rafael J. Wysocki wrote: > On Thu, Jan 4, 2024 at 1:04 PM Russell King (Oracle) > <linux@armlinux.org.uk> wrote: > > > > On Thu, Jan 04, 2024 at 11:34:48AM +0000, Marc Zyngier wrote: > > > On Wed, 03 Jan 2024 13:43:16 +0000, > > > "Rafael J. Wysocki" <rafael@kernel.org> wrote: > > > > > > > > On Wed, Dec 27, 2023 at 12:00 PM Lorenzo Pieralisi > > > > <lpieralisi@kernel.org> wrote: > > > > > > > > > > This series is v4 of previous series: > > > > > > > > > > v3: https://lore.kernel.org/all/20231006125929.48591-1-lpieralisi@kernel.org > > > > > v2: https://lore.kernel.org/all/20230906094139.16032-1-lpieralisi@kernel.org > > > > > v1: https://lore.kernel.org/all/20230905104721.52199-1-lpieralisi@kernel.org > > > > > > > > > > v3 -> v4: > > > > > - Dropped patches [1-3], already merged > > > > > - Added Linuxized ACPICA changes accepted upstream > > > > > - Rebased against v6.7-rc3 > > > > > > > > > > v2 -> v3: > > > > > - Added ACPICA temporary changes and ACPI changes to implement > > > > > ECR https://bugzilla.tianocore.org/show_bug.cgi?id=4557 > > > > > - ACPI changes are for testing purposes - subject to ECR code > > > > > first approval > > > > > > > > > > v1 -> v2: > > > > > - Updated DT bindings as per feedback > > > > > - Updated patch[2] to use GIC quirks infrastructure > > > > > > > > > > Original cover letter > > > > > --- > > > > > The GICv3 architecture specifications provide a means for the > > > > > system programmer to set the shareability and cacheability > > > > > attributes the GIC components (redistributors and ITSes) use > > > > > to drive memory transactions. > > > > > > > > > > Albeit the architecture give control over shareability/cacheability > > > > > memory transactions attributes (and barriers), it is allowed to > > > > > connect the GIC interconnect ports to non-coherent memory ports > > > > > on the interconnect, basically tying off shareability/cacheability > > > > > "wires" and de-facto making the redistributors and ITSes non-coherent > > > > > memory observers. > > > > > > > > > > This series aims at starting a discussion over a possible solution > > > > > to this problem, by adding to the GIC device tree bindings the > > > > > standard dma-noncoherent property. The GIC driver uses the property > > > > > to force the redistributors and ITSes shareability attributes to > > > > > non-shareable, which consequently forces the driver to use CMOs > > > > > on GIC memory tables. > > > > > > > > > > On ARM DT DMA is default non-coherent, so the GIC driver can't rely > > > > > on the generic DT dma-coherent/non-coherent property management layer > > > > > (of_dma_is_coherent()) which would default all GIC designs in the field > > > > > as non-coherent; it has to rely on ad-hoc dma-noncoherent property handling. > > > > > > > > > > When a consistent approach is agreed upon for DT an equivalent binding will > > > > > be put forward for ACPI based systems. > > > > > > > > > > Lorenzo Pieralisi (3): > > > > > ACPICA: MADT: Add GICC online capable bit handling > > > > > ACPICA: MADT: Add new MADT GICC/GICR/ITS non-coherent flags handling > > > > > irqchip/gic-v3: Enable non-coherent redistributors/ITSes ACPI probing > > > > > > > > > > drivers/acpi/processor_core.c | 21 +++++++++++++++++++++ > > > > > drivers/irqchip/irq-gic-common.h | 8 ++++++++ > > > > > drivers/irqchip/irq-gic-v3-its.c | 4 ++++ > > > > > drivers/irqchip/irq-gic-v3.c | 9 +++++++++ > > > > > include/acpi/actbl2.h | 12 ++++++++++-- > > > > > include/linux/acpi.h | 3 +++ > > > > > 6 files changed, 55 insertions(+), 2 deletions(-) > > > > > > > > > > -- > > > > > > > > I can apply the first 2 patches, but I would need an ACK for the 3rd one. > > > > > > > > Alternatively, feel free to add > > > > > > > > Acked-by: Rafael J. Wysocki <rafael.j.wysocki@intel.com> > > > > > > > > to the first 2 patches and route them via ARM64. > > > > > > Thanks for that. I have some comments on the third patch, which I'd > > > like to see addressed beforehand. This is probably all 6.9 material > > > anyway (nobody is affected by this so far). > > > > From a purely selfish point of view, it would be useful to have the > > first patch merged merely to reduce the burden of patches for vcpu > > hotplug. > > OK, since there will be at least one more iteration of patch [3/3] > AFAICS, I'll queue up patches [1-2/3] for 6.8 (next week, though). Thank you Rafael. Lorenzo