Message ID | 20231223182932.27683-1-jason-jh.lin@mediatek.com |
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Headers |
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[2604:1380:40f1:3f00::1]) by mx.google.com with ESMTPS id i18-20020aa79092000000b006cbd40b46basi5183127pfa.133.2023.12.23.10.35.33 for <ouuuleilei@gmail.com> (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 23 Dec 2023 10:35:34 -0800 (PST) Received-SPF: pass (google.com: domain of linux-kernel+bounces-10543-ouuuleilei=gmail.com@vger.kernel.org designates 2604:1380:40f1:3f00::1 as permitted sender) client-ip=2604:1380:40f1:3f00::1; Authentication-Results: mx.google.com; dkim=pass header.i=@mediatek.com header.s=dk header.b=DIh3bXCt; spf=pass (google.com: domain of linux-kernel+bounces-10543-ouuuleilei=gmail.com@vger.kernel.org designates 2604:1380:40f1:3f00::1 as permitted sender) smtp.mailfrom="linux-kernel+bounces-10543-ouuuleilei=gmail.com@vger.kernel.org"; dmarc=pass (p=QUARANTINE sp=QUARANTINE dis=NONE) header.from=mediatek.com Received: from smtp.subspace.kernel.org (wormhole.subspace.kernel.org [52.25.139.140]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by sy.mirrors.kernel.org (Postfix) with ESMTPS id DA669B22D14 for <ouuuleilei@gmail.com>; Sat, 23 Dec 2023 18:33:50 +0000 (UTC) Received: from localhost.localdomain (localhost.localdomain [127.0.0.1]) by smtp.subspace.kernel.org (Postfix) with ESMTP id 2F09F28DDF; Sat, 23 Dec 2023 18:29:54 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=mediatek.com header.i=@mediatek.com header.b="DIh3bXCt" X-Original-To: linux-kernel@vger.kernel.org Received: from mailgw01.mediatek.com (unknown [60.244.123.138]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 732DA2208A; Sat, 23 Dec 2023 18:29:49 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=mediatek.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=mediatek.com X-UUID: 38ff171ca1c111eea5db2bebc7c28f94-20231224 DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=mediatek.com; s=dk; h=Content-Type:MIME-Version:Message-ID:Date:Subject:CC:To:From; bh=3gOWOBV0rgKU+/PmGI3xj46A8m8R3ijvR09XFgFjDzI=; b=DIh3bXCtN/fYiNVanoR0oH/u095iil8OqB/bV4Ft11zdeqJ12vybbNzJidSozVn3CCkudYBJgiujZct5pog0dsIYcYxeUk9MW/azE3v4dg9N9yzYKPcmSofJJUpYyb5VE7BroAW9Mfmq2QGMqUayH05wxOaRld/LAncd4v8lU8U=; X-CID-P-RULE: Release_Ham X-CID-O-INFO: VERSION:1.1.35,REQID:9436a27a-c04f-4c20-8cee-848bfa2f11fc,IP:0,U RL:0,TC:0,Content:0,EDM:0,RT:0,SF:0,FILE:0,BULK:0,RULE:Release_Ham,ACTION: release,TS:0 X-CID-META: VersionHash:5d391d7,CLOUDID:a65d7f8d-e2c0-40b0-a8fe-7c7e47299109,B ulkID:nil,BulkQuantity:0,Recheck:0,SF:102,TC:nil,Content:0,EDM:-3,IP:nil,U RL:1,File:nil,Bulk:nil,QS:nil,BEC:nil,COL:0,OSI:0,OSA:0,AV:0,LES:1,SPR:NO, DKR:0,DKP:0,BRR:0,BRE:0 X-CID-BVR: 0 X-CID-BAS: 0,_,0,_ X-CID-FACTOR: TF_CID_SPAM_SNR,TF_CID_SPAM_ULS X-UUID: 38ff171ca1c111eea5db2bebc7c28f94-20231224 Received: from mtkmbs13n1.mediatek.inc [(172.21.101.193)] by mailgw01.mediatek.com (envelope-from <jason-jh.lin@mediatek.com>) (Generic MTA with TLSv1.2 ECDHE-RSA-AES256-GCM-SHA384 256/256) with ESMTP id 1914793848; Sun, 24 Dec 2023 02:29:35 +0800 Received: from mtkmbs11n1.mediatek.inc (172.21.101.185) by mtkmbs11n1.mediatek.inc (172.21.101.185) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1118.26; Sun, 24 Dec 2023 02:29:33 +0800 Received: from mtksdccf07.mediatek.inc (172.21.84.99) by mtkmbs11n1.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.2.1118.26 via Frontend Transport; Sun, 24 Dec 2023 02:29:33 +0800 From: Jason-JH.Lin <jason-jh.lin@mediatek.com> To: Rob Herring <robh+dt@kernel.org>, Krzysztof Kozlowski <krzysztof.kozlowski+dt@linaro.org>, Conor Dooley <conor+dt@kernel.org>, Matthias Brugger <matthias.bgg@gmail.com>, AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>, Chun-Kuang Hu <chunkuang.hu@kernel.org> CC: <devicetree@vger.kernel.org>, <linux-kernel@vger.kernel.org>, <linux-arm-kernel@lists.infradead.org>, <linux-mediatek@lists.infradead.org>, <dri-devel@lists.freedesktop.org>, <linux-media@vger.kernel.org>, <linaro-mm-sig@lists.linaro.org>, Jason-ch Chen <jason-ch.chen@mediatek.com>, Johnson Wang <johnson.wang@mediatek.com>, "Jason-JH . Lin" <jason-jh.lin@mediatek.com>, Singo Chang <singo.chang@mediatek.com>, Nancy Lin <nancy.lin@mediatek.com>, Shawn Sung <shawn.sung@mediatek.com>, <Project_Global_Chrome_Upstream_Group@mediatek.com>, Jeffrey Kardatzke <jkardatzke@google.com>, Jason-jh Lin <jason-jh.lin@mediatek.corp-partner.google.com> Subject: [PATCH v3 00/11] Add mediate-drm secure flow for SVP Date: Sun, 24 Dec 2023 02:29:21 +0800 Message-ID: <20231223182932.27683-1-jason-jh.lin@mediatek.com> X-Mailer: git-send-email 2.18.0 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: <linux-kernel.vger.kernel.org> List-Subscribe: <mailto:linux-kernel+subscribe@vger.kernel.org> List-Unsubscribe: <mailto:linux-kernel+unsubscribe@vger.kernel.org> MIME-Version: 1.0 Content-Type: text/plain X-MTK: N X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1786098781406215055 X-GMAIL-MSGID: 1786098781406215055 |
Series |
Add mediate-drm secure flow for SVP
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Message
Jason-JH Lin (林睿祥)
Dec. 23, 2023, 6:29 p.m. UTC
From: Jason-jh Lin <jason-jh.lin@mediatek.corp-partner.google.com>
Memory Definitions:
secure memory - Memory allocated in the TEE (Trusted Execution
Environment) which is inaccessible in the REE (Rich Execution
Environment, i.e. linux kernel/userspace).
secure handle - Integer value which acts as reference to 'secure
memory'. Used in communication between TEE and REE to reference
'secure memory'.
secure buffer - 'secure memory' that is used to store decrypted,
compressed video or for other general purposes in the TEE.
secure surface - 'secure memory' that is used to store graphic buffers.
Memory Usage in SVP:
The overall flow of SVP starts with encrypted video coming in from an
outside source into the REE. The REE will then allocate a 'secure
buffer' and send the corresponding 'secure handle' along with the
encrypted, compressed video data to the TEE. The TEE will then decrypt
the video and store the result in the 'secure buffer'. The REE will
then allocate a 'secure surface'. The REE will pass the 'secure
handles' for both the 'secure buffer' and 'secure surface' into the
TEE for video decoding. The video decoder HW will then decode the
contents of the 'secure buffer' and place the result in the 'secure
surface'. The REE will then attach the 'secure surface' to the overlay
plane for rendering of the video.
Everything relating to ensuring security of the actual contents of the
'secure buffer' and 'secure surface' is out of scope for the REE and
is the responsibility of the TEE.
DRM driver handles allocation of gem objects that are backed by a 'secure
surface' and for displaying a 'secure surface' on the overlay plane.
This introduces a new flag for object creation called
DRM_MTK_GEM_CREATE_ENCRYPTED which indicates it should be a 'secure
surface'. All changes here are in MediaTek specific code.
---
TODO:
1) Remove get sec larb port interface in ddp_comp, ovl and ovl_adaptor.
2) Verify instruction for enabling/disabling dapc and larb port in TEE
drop the sec_engine flags in normal world and.
3) Move DISP_REG_OVL_SECURE setting to secure world for mtk_disp_ovl.c.
4) Change the parameter register address in mtk_ddp_sec_write()
from "u32 addr" to "struct cmdq_client_reg *cmdq_reg".
5) Implement setting mmsys routing table in the secure world series.
---
Based on 5 series and 1 patch:
[1] v3 dma-buf: heaps: Add MediaTek secure heap
- https://patchwork.kernel.org/project/linux-mediatek/list/?series=809023
[2] v3 add driver to support secure video decoder
- https://patchwork.kernel.org/project/linux-mediatek/list/?series=807308
[3] v4 soc: mediatek: Add register definitions for GCE
- https://patchwork.kernel.org/project/linux-mediatek/patch/20231212121957.19231-2-shawn.sung@mediatek.com/
[4] v2 Add CMDQ driver support for mt8188
- https://patchwork.kernel.org/project/linux-mediatek/list/?series=810302
[5] Add mediatek,gce-events definition to mediatek,gce-mailbox bindings
- https://patchwork.kernel.org/project/linux-mediatek/list/?series=810938
[6] v3 Add CMDQ secure driver for SVP
- https://patchwork.kernel.org/project/linux-mediatek/list/?series=812379
---
Change in v3:
1. fix kerneldoc problems
2. fix typo in title and commit message
3. adjust naming for secure variable
4. add the missing part for is_suecure plane implementation
5. use BIT_ULL macro to replace bit shifting
6. move modification of ovl_adaptor part to the correct patch
7. add TODO list in commit message
8. add commit message for using share memory to store execute count
Change in v2:
1. remove the DRIVER_RDNDER flag for mtk_drm_ioctl
2. move cmdq_insert_backup_cookie into client driver
3. move secure gce node define from mt8195-cherry.dtsi to mt8195.dtsi
---
CK Hu (1):
drm/mediatek: Add interface to allocate MediaTek GEM buffer.
Jason-JH.Lin (10):
drm/mediatek/uapi: Add DRM_MTK_GEM_CREATE_ENCRYPTED flag
drm/mediatek: Add secure buffer control flow to mtk_drm_gem
drm/mediatek: Add secure identify flag and funcution to mtk_drm_plane
drm/mediatek: Add mtk_ddp_sec_write to config secure buffer info
drm/mediatek: Add get_sec_port interface to mtk_ddp_comp
drm/mediatek: Add secure layer config support for ovl
drm/mediatek: Add secure layer config support for ovl_adaptor
drm/mediatek: Add secure flow support to mediatek-drm
drm/mediatek: Add cmdq_insert_backup_cookie before secure pkt finalize
arm64: dts: mt8195: Add secure mbox settings for vdosys
arch/arm64/boot/dts/mediatek/mt8195.dtsi | 6 +-
drivers/gpu/drm/mediatek/mtk_disp_drv.h | 3 +
drivers/gpu/drm/mediatek/mtk_disp_ovl.c | 31 +-
.../gpu/drm/mediatek/mtk_disp_ovl_adaptor.c | 15 +
drivers/gpu/drm/mediatek/mtk_drm_crtc.c | 274 +++++++++++++++++-
drivers/gpu/drm/mediatek/mtk_drm_crtc.h | 1 +
drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c | 30 ++
drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h | 14 +
drivers/gpu/drm/mediatek/mtk_drm_drv.c | 13 +
drivers/gpu/drm/mediatek/mtk_drm_gem.c | 122 ++++++++
drivers/gpu/drm/mediatek/mtk_drm_gem.h | 16 +
drivers/gpu/drm/mediatek/mtk_drm_plane.c | 26 ++
drivers/gpu/drm/mediatek/mtk_drm_plane.h | 2 +
drivers/gpu/drm/mediatek/mtk_mdp_rdma.c | 11 +-
drivers/gpu/drm/mediatek/mtk_mdp_rdma.h | 2 +
include/uapi/drm/mediatek_drm.h | 59 ++++
16 files changed, 607 insertions(+), 18 deletions(-)
create mode 100644 include/uapi/drm/mediatek_drm.h
Comments
Hi, Jason: On Sun, 2023-12-24 at 02:29 +0800, Jason-JH.Lin wrote: > From: Jason-jh Lin <jason-jh.lin@mediatek.corp-partner.google.com> > > Memory Definitions: > secure memory - Memory allocated in the TEE (Trusted Execution > Environment) which is inaccessible in the REE (Rich Execution > Environment, i.e. linux kernel/userspace). > secure handle - Integer value which acts as reference to 'secure > memory'. Used in communication between TEE and REE to reference > 'secure memory'. > secure buffer - 'secure memory' that is used to store decrypted, > compressed video or for other general purposes in the TEE. > secure surface - 'secure memory' that is used to store graphic > buffers. > > Memory Usage in SVP: > The overall flow of SVP starts with encrypted video coming in from an > outside source into the REE. The REE will then allocate a 'secure > buffer' and send the corresponding 'secure handle' along with the > encrypted, compressed video data to the TEE. The TEE will then > decrypt > the video and store the result in the 'secure buffer'. The REE will > then allocate a 'secure surface'. The REE will pass the 'secure > handles' for both the 'secure buffer' and 'secure surface' into the > TEE for video decoding. The video decoder HW will then decode the > contents of the 'secure buffer' and place the result in the 'secure > surface'. The REE will then attach the 'secure surface' to the > overlay > plane for rendering of the video. > > Everything relating to ensuring security of the actual contents of > the > 'secure buffer' and 'secure surface' is out of scope for the REE and > is the responsibility of the TEE. > > DRM driver handles allocation of gem objects that are backed by a > 'secure > surface' and for displaying a 'secure surface' on the overlay plane. > This introduces a new flag for object creation called > DRM_MTK_GEM_CREATE_ENCRYPTED which indicates it should be a 'secure > surface'. All changes here are in MediaTek specific code. I would like to decouple secure display and secure decode. One reason is that I would like secure display could be tested itself without secure decode. Another reason is that if someone has draw an image and want to display securely, this is not related to decode. To achieve this, mediatek drm driver should provide render function on secure surface. The most simple function is to bitblt a normal surface onto secure surface. User could allocate both normal surface and secure surface, draw on normal surface and bitblt normal surface onto secure surface. We could have limitation that normal surface and secure surface have the same width, height, pitch, pixel format, and the bitblt is the full image bitblt. So mediatek drm driver just need a TEE function that do memory copy from normal surface to secure surface. This is not a must-be function, but it has some benefit for secure display. Regards, CK > --- > TODO: > 1) Remove get sec larb port interface in ddp_comp, ovl and > ovl_adaptor. > 2) Verify instruction for enabling/disabling dapc and larb port in > TEE > drop the sec_engine flags in normal world and. > 3) Move DISP_REG_OVL_SECURE setting to secure world for > mtk_disp_ovl.c. > 4) Change the parameter register address in mtk_ddp_sec_write() > from "u32 addr" to "struct cmdq_client_reg *cmdq_reg". > 5) Implement setting mmsys routing table in the secure world series. > --- > Based on 5 series and 1 patch: > [1] v3 dma-buf: heaps: Add MediaTek secure heap > - > https://urldefense.com/v3/__https://patchwork.kernel.org/project/linux-mediatek/list/?series=809023__;!!CTRNKA9wMg0ARbw!lYGWfjjIBlxJvwBXWyxHTyc2vew5YagqT_qJZrYONTH20h95qxC3PH9V91vjplYU3S0ayseyHpxRQFSqATHgDnU$ > > [2] v3 add driver to support secure video decoder > - > https://urldefense.com/v3/__https://patchwork.kernel.org/project/linux-mediatek/list/?series=807308__;!!CTRNKA9wMg0ARbw!lYGWfjjIBlxJvwBXWyxHTyc2vew5YagqT_qJZrYONTH20h95qxC3PH9V91vjplYU3S0ayseyHpxRQFSq9TXMSIQ$ > > [3] v4 soc: mediatek: Add register definitions for GCE > - > https://urldefense.com/v3/__https://patchwork.kernel.org/project/linux-mediatek/patch/20231212121957.19231-2-shawn.sung@mediatek.com/__;!!CTRNKA9wMg0ARbw!lYGWfjjIBlxJvwBXWyxHTyc2vew5YagqT_qJZrYONTH20h95qxC3PH9V91vjplYU3S0ayseyHpxRQFSqkO4_0ac$ > > [4] v2 Add CMDQ driver support for mt8188 > - > https://urldefense.com/v3/__https://patchwork.kernel.org/project/linux-mediatek/list/?series=810302__;!!CTRNKA9wMg0ARbw!lYGWfjjIBlxJvwBXWyxHTyc2vew5YagqT_qJZrYONTH20h95qxC3PH9V91vjplYU3S0ayseyHpxRQFSqcXdKnXU$ > > [5] Add mediatek,gce-events definition to mediatek,gce-mailbox > bindings > - > https://urldefense.com/v3/__https://patchwork.kernel.org/project/linux-mediatek/list/?series=810938__;!!CTRNKA9wMg0ARbw!lYGWfjjIBlxJvwBXWyxHTyc2vew5YagqT_qJZrYONTH20h95qxC3PH9V91vjplYU3S0ayseyHpxRQFSqqGM08aE$ > > [6] v3 Add CMDQ secure driver for SVP > - > https://urldefense.com/v3/__https://patchwork.kernel.org/project/linux-mediatek/list/?series=812379__;!!CTRNKA9wMg0ARbw!lYGWfjjIBlxJvwBXWyxHTyc2vew5YagqT_qJZrYONTH20h95qxC3PH9V91vjplYU3S0ayseyHpxRQFSq_YXTH9A$ > > --- > Change in v3: > 1. fix kerneldoc problems > 2. fix typo in title and commit message > 3. adjust naming for secure variable > 4. add the missing part for is_suecure plane implementation > 5. use BIT_ULL macro to replace bit shifting > 6. move modification of ovl_adaptor part to the correct patch > 7. add TODO list in commit message > 8. add commit message for using share memory to store execute count > > Change in v2: > > 1. remove the DRIVER_RDNDER flag for mtk_drm_ioctl > 2. move cmdq_insert_backup_cookie into client driver > 3. move secure gce node define from mt8195-cherry.dtsi to mt8195.dtsi > --- > CK Hu (1): > drm/mediatek: Add interface to allocate MediaTek GEM buffer. > > Jason-JH.Lin (10): > drm/mediatek/uapi: Add DRM_MTK_GEM_CREATE_ENCRYPTED flag > drm/mediatek: Add secure buffer control flow to mtk_drm_gem > drm/mediatek: Add secure identify flag and funcution to > mtk_drm_plane > drm/mediatek: Add mtk_ddp_sec_write to config secure buffer info > drm/mediatek: Add get_sec_port interface to mtk_ddp_comp > drm/mediatek: Add secure layer config support for ovl > drm/mediatek: Add secure layer config support for ovl_adaptor > drm/mediatek: Add secure flow support to mediatek-drm > drm/mediatek: Add cmdq_insert_backup_cookie before secure pkt > finalize > arm64: dts: mt8195: Add secure mbox settings for vdosys > > arch/arm64/boot/dts/mediatek/mt8195.dtsi | 6 +- > drivers/gpu/drm/mediatek/mtk_disp_drv.h | 3 + > drivers/gpu/drm/mediatek/mtk_disp_ovl.c | 31 +- > .../gpu/drm/mediatek/mtk_disp_ovl_adaptor.c | 15 + > drivers/gpu/drm/mediatek/mtk_drm_crtc.c | 274 > +++++++++++++++++- > drivers/gpu/drm/mediatek/mtk_drm_crtc.h | 1 + > drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c | 30 ++ > drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h | 14 + > drivers/gpu/drm/mediatek/mtk_drm_drv.c | 13 + > drivers/gpu/drm/mediatek/mtk_drm_gem.c | 122 ++++++++ > drivers/gpu/drm/mediatek/mtk_drm_gem.h | 16 + > drivers/gpu/drm/mediatek/mtk_drm_plane.c | 26 ++ > drivers/gpu/drm/mediatek/mtk_drm_plane.h | 2 + > drivers/gpu/drm/mediatek/mtk_mdp_rdma.c | 11 +- > drivers/gpu/drm/mediatek/mtk_mdp_rdma.h | 2 + > include/uapi/drm/mediatek_drm.h | 59 ++++ > 16 files changed, 607 insertions(+), 18 deletions(-) > create mode 100644 include/uapi/drm/mediatek_drm.h >
Hi CK, Thanks for the reviews. On Thu, 2023-12-28 at 06:27 +0000, CK Hu (胡俊光) wrote: > Hi, Jason: > > On Sun, 2023-12-24 at 02:29 +0800, Jason-JH.Lin wrote: > > From: Jason-jh Lin <jason-jh.lin@mediatek.corp-partner.google.com> > > > > Memory Definitions: > > secure memory - Memory allocated in the TEE (Trusted Execution > > Environment) which is inaccessible in the REE (Rich Execution > > Environment, i.e. linux kernel/userspace). > > secure handle - Integer value which acts as reference to 'secure > > memory'. Used in communication between TEE and REE to reference > > 'secure memory'. > > secure buffer - 'secure memory' that is used to store decrypted, > > compressed video or for other general purposes in the TEE. > > secure surface - 'secure memory' that is used to store graphic > > buffers. > > > > Memory Usage in SVP: > > The overall flow of SVP starts with encrypted video coming in from > > an > > outside source into the REE. The REE will then allocate a 'secure > > buffer' and send the corresponding 'secure handle' along with the > > encrypted, compressed video data to the TEE. The TEE will then > > decrypt > > the video and store the result in the 'secure buffer'. The REE will > > then allocate a 'secure surface'. The REE will pass the 'secure > > handles' for both the 'secure buffer' and 'secure surface' into the > > TEE for video decoding. The video decoder HW will then decode the > > contents of the 'secure buffer' and place the result in the 'secure > > surface'. The REE will then attach the 'secure surface' to the > > overlay > > plane for rendering of the video. > > > > Everything relating to ensuring security of the actual contents of > > the > > 'secure buffer' and 'secure surface' is out of scope for the REE > > and > > is the responsibility of the TEE. > > > > DRM driver handles allocation of gem objects that are backed by a > > 'secure > > surface' and for displaying a 'secure surface' on the overlay > > plane. > > This introduces a new flag for object creation called > > DRM_MTK_GEM_CREATE_ENCRYPTED which indicates it should be a 'secure > > surface'. All changes here are in MediaTek specific code. > > I would like to decouple secure display and secure decode. One reason > is that I would like secure display could be tested itself without > secure decode. Another reason is that if someone has draw an image > and > want to display securely, this is not related to decode. > > To achieve this, mediatek drm driver should provide render function > on > secure surface. The most simple function is to bitblt a normal > surface > onto secure surface. User could allocate both normal surface and > secure > surface, draw on normal surface and bitblt normal surface onto secure > surface. We could have limitation that normal surface and secure > surface have the same width, height, pitch, pixel format, and the > bitblt is the full image bitblt. So mediatek drm driver just need a > TEE > function that do memory copy from normal surface to secure surface. > > This is not a must-be function, but it has some benefit for secure > display. > > Regards, > CK > OK, I'll also add this to TODO. Regards, Jason-JH.Lin > > --- > > TODO: > > 1) Remove get sec larb port interface in ddp_comp, ovl and > > ovl_adaptor. > > 2) Verify instruction for enabling/disabling dapc and larb port in > > TEE > > drop the sec_engine flags in normal world and. > > 3) Move DISP_REG_OVL_SECURE setting to secure world for > > mtk_disp_ovl.c. > > 4) Change the parameter register address in mtk_ddp_sec_write() > > from "u32 addr" to "struct cmdq_client_reg *cmdq_reg". > > 5) Implement setting mmsys routing table in the secure world > > series. > > --- > > Based on 5 series and 1 patch: > > [1] v3 dma-buf: heaps: Add MediaTek secure heap > > - > > https://urldefense.com/v3/__https://patchwork.kernel.org/project/linux-mediatek/list/?series=809023__;!!CTRNKA9wMg0ARbw!lYGWfjjIBlxJvwBXWyxHTyc2vew5YagqT_qJZrYONTH20h95qxC3PH9V91vjplYU3S0ayseyHpxRQFSqATHgDnU$ > > > > [2] v3 add driver to support secure video decoder > > - > > https://urldefense.com/v3/__https://patchwork.kernel.org/project/linux-mediatek/list/?series=807308__;!!CTRNKA9wMg0ARbw!lYGWfjjIBlxJvwBXWyxHTyc2vew5YagqT_qJZrYONTH20h95qxC3PH9V91vjplYU3S0ayseyHpxRQFSq9TXMSIQ$ > > > > [3] v4 soc: mediatek: Add register definitions for GCE > > - > > https://urldefense.com/v3/__https://patchwork.kernel.org/project/linux-mediatek/patch/20231212121957.19231-2-shawn.sung@mediatek.com/__;!!CTRNKA9wMg0ARbw!lYGWfjjIBlxJvwBXWyxHTyc2vew5YagqT_qJZrYONTH20h95qxC3PH9V91vjplYU3S0ayseyHpxRQFSqkO4_0ac$ > > > > [4] v2 Add CMDQ driver support for mt8188 > > - > > https://urldefense.com/v3/__https://patchwork.kernel.org/project/linux-mediatek/list/?series=810302__;!!CTRNKA9wMg0ARbw!lYGWfjjIBlxJvwBXWyxHTyc2vew5YagqT_qJZrYONTH20h95qxC3PH9V91vjplYU3S0ayseyHpxRQFSqcXdKnXU$ > > > > [5] Add mediatek,gce-events definition to mediatek,gce-mailbox > > bindings > > - > > https://urldefense.com/v3/__https://patchwork.kernel.org/project/linux-mediatek/list/?series=810938__;!!CTRNKA9wMg0ARbw!lYGWfjjIBlxJvwBXWyxHTyc2vew5YagqT_qJZrYONTH20h95qxC3PH9V91vjplYU3S0ayseyHpxRQFSqqGM08aE$ > > > > [6] v3 Add CMDQ secure driver for SVP > > - > > https://urldefense.com/v3/__https://patchwork.kernel.org/project/linux-mediatek/list/?series=812379__;!!CTRNKA9wMg0ARbw!lYGWfjjIBlxJvwBXWyxHTyc2vew5YagqT_qJZrYONTH20h95qxC3PH9V91vjplYU3S0ayseyHpxRQFSq_YXTH9A$ > > > > --- > > Change in v3: > > 1. fix kerneldoc problems > > 2. fix typo in title and commit message > > 3. adjust naming for secure variable > > 4. add the missing part for is_suecure plane implementation > > 5. use BIT_ULL macro to replace bit shifting > > 6. move modification of ovl_adaptor part to the correct patch > > 7. add TODO list in commit message > > 8. add commit message for using share memory to store execute count > > > > Change in v2: > > > > 1. remove the DRIVER_RDNDER flag for mtk_drm_ioctl > > 2. move cmdq_insert_backup_cookie into client driver > > 3. move secure gce node define from mt8195-cherry.dtsi to > > mt8195.dtsi > > --- > > CK Hu (1): > > drm/mediatek: Add interface to allocate MediaTek GEM buffer. > > > > Jason-JH.Lin (10): > > drm/mediatek/uapi: Add DRM_MTK_GEM_CREATE_ENCRYPTED flag > > drm/mediatek: Add secure buffer control flow to mtk_drm_gem > > drm/mediatek: Add secure identify flag and funcution to > > mtk_drm_plane > > drm/mediatek: Add mtk_ddp_sec_write to config secure buffer info > > drm/mediatek: Add get_sec_port interface to mtk_ddp_comp > > drm/mediatek: Add secure layer config support for ovl > > drm/mediatek: Add secure layer config support for ovl_adaptor > > drm/mediatek: Add secure flow support to mediatek-drm > > drm/mediatek: Add cmdq_insert_backup_cookie before secure pkt > > finalize > > arm64: dts: mt8195: Add secure mbox settings for vdosys > > > > arch/arm64/boot/dts/mediatek/mt8195.dtsi | 6 +- > > drivers/gpu/drm/mediatek/mtk_disp_drv.h | 3 + > > drivers/gpu/drm/mediatek/mtk_disp_ovl.c | 31 +- > > .../gpu/drm/mediatek/mtk_disp_ovl_adaptor.c | 15 + > > drivers/gpu/drm/mediatek/mtk_drm_crtc.c | 274 > > +++++++++++++++++- > > drivers/gpu/drm/mediatek/mtk_drm_crtc.h | 1 + > > drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c | 30 ++ > > drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h | 14 + > > drivers/gpu/drm/mediatek/mtk_drm_drv.c | 13 + > > drivers/gpu/drm/mediatek/mtk_drm_gem.c | 122 ++++++++ > > drivers/gpu/drm/mediatek/mtk_drm_gem.h | 16 + > > drivers/gpu/drm/mediatek/mtk_drm_plane.c | 26 ++ > > drivers/gpu/drm/mediatek/mtk_drm_plane.h | 2 + > > drivers/gpu/drm/mediatek/mtk_mdp_rdma.c | 11 +- > > drivers/gpu/drm/mediatek/mtk_mdp_rdma.h | 2 + > > include/uapi/drm/mediatek_drm.h | 59 ++++ > > 16 files changed, 607 insertions(+), 18 deletions(-) > > create mode 100644 include/uapi/drm/mediatek_drm.h > >