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[2604:1380:40f1:3f00::1]) by mx.google.com with ESMTPS id bn3-20020a056a02030300b005cd98356ccfsi1368833pgb.760.2023.12.21.01.56.50 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 21 Dec 2023 01:56:51 -0800 (PST) Received-SPF: pass (google.com: domain of linux-kernel+bounces-8142-ouuuleilei=gmail.com@vger.kernel.org designates 2604:1380:40f1:3f00::1 as permitted sender) client-ip=2604:1380:40f1:3f00::1; Authentication-Results: mx.google.com; dkim=pass header.i=@intel.com header.s=Intel header.b=kCFdrBkF; spf=pass (google.com: domain of linux-kernel+bounces-8142-ouuuleilei=gmail.com@vger.kernel.org designates 2604:1380:40f1:3f00::1 as permitted sender) smtp.mailfrom="linux-kernel+bounces-8142-ouuuleilei=gmail.com@vger.kernel.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=intel.com Received: from smtp.subspace.kernel.org (wormhole.subspace.kernel.org [52.25.139.140]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by sy.mirrors.kernel.org (Postfix) with ESMTPS id E74DCB27239 for ; Thu, 21 Dec 2023 09:38:43 +0000 (UTC) Received: from localhost.localdomain (localhost.localdomain [127.0.0.1]) by smtp.subspace.kernel.org (Postfix) with ESMTP id B2E3A4D111; Thu, 21 Dec 2023 09:33:07 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b="kCFdrBkF" X-Original-To: linux-kernel@vger.kernel.org Received: from mgamail.intel.com (mgamail.intel.com [198.175.65.12]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id AECDD4C3CD; Thu, 21 Dec 2023 09:33:02 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=intel.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=intel.com DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1703151182; x=1734687182; h=from:to:cc:subject:date:message-id:mime-version: content-transfer-encoding; bh=RNfmASP2goLFqQvl0CMtUIBdraEA3ADsaIbtIGPBOE4=; b=kCFdrBkFWkh9rs6uEA4wopi062hNIcV+MXQhYdvipCiV1QwA4IqDings EXoO+oyPsBHlOaxb1x7N4N+BIhews9CcY4WHjhSIRMEHr+NdtQUjyBBVV HDcmNCfLyZlukP+cYOzSABj0nGUQRUougMyPHuA6dBZqP9fOb5hV+rSiP /DKXe/JnQm9HMv8/xVVjuXuK0H2hjZTAUnBB1uXouBLNU61FaLQhkTAGW 6I/SGE6PHme/8ZQvsJ45Y/jM0nP8riyMSfqg/ipDuYhBWb5nEpT3rm/TK opHlJT7TOhhtPKsxIKldQgeODhd8MOTRR+G6AKTaFvJJd0U06voQ9cyOe A==; X-IronPort-AV: E=McAfee;i="6600,9927,10930"; a="3188441" X-IronPort-AV: E=Sophos;i="6.04,293,1695711600"; d="scan'208";a="3188441" Received: from orsmga001.jf.intel.com ([10.7.209.18]) by orvoesa104.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 21 Dec 2023 01:33:02 -0800 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6600,9927,10930"; a="810918114" X-IronPort-AV: E=Sophos;i="6.04,293,1695711600"; d="scan'208";a="810918114" Received: from inlubt0316.iind.intel.com ([10.191.20.213]) by orsmga001.jf.intel.com with ESMTP; 21 Dec 2023 01:32:55 -0800 From: lakshmi.sowjanya.d@intel.com To: tglx@linutronix.de, jstultz@google.com, giometti@enneenne.com, corbet@lwn.net, linux-kernel@vger.kernel.org Cc: x86@kernel.org, netdev@vger.kernel.org, linux-doc@vger.kernel.org, intel-wired-lan@lists.osuosl.org, andriy.shevchenko@linux.intel.com, eddie.dong@intel.com, christopher.s.hall@intel.com, jesse.brandeburg@intel.com, davem@davemloft.net, alexandre.torgue@foss.st.com, joabreu@synopsys.com, mcoquelin.stm32@gmail.com, perex@perex.cz, linux-sound@vger.kernel.org, anthony.l.nguyen@intel.com, pandith.n@intel.com, mallikarjunappa.sangannavar@intel.com, thejesh.reddy.t.r@intel.com, lakshmi.sowjanya.d@intel.com Subject: [RFC PATCH v2 00/10] Add support for Intel PPS Generator Date: Thu, 21 Dec 2023 15:02:44 +0530 Message-Id: <20231221093254.9599-1-lakshmi.sowjanya.d@intel.com> X-Mailer: git-send-email 2.35.3 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1785884952153832367 X-GMAIL-MSGID: 1785884952153832367 From: Lakshmi Sowjanya D The goal of the PPS(Pulse Per Second) hardware/software is to generate a signal from the system on a wire so that some third-party hardware can observe that signal and judge how close the system's time is to another system or piece of hardware. Existing methods (like parallel ports) require software to flip a bit at just the right time to create a PPS signal. Many things can prevent software from doing this precisely. This (Timed I/O) method is better because software only "arms" the hardware in advance and then depends on the hardware to "fire" and flip the signal at just the right time. To generate a PPS signal with this new hardware, the kernel wakes up twice a second, once for 1->0 edge and other for the 0->1 edge. It does this shortly (~10ms) before the actual change in the signal needs to be made. It computes the TSC value at which edge will happen, convert to a value hardware understands and program this value to Timed I/O hardware. The actual edge transition happens without any further action from the kernel. The result here is a signal coming out of the system that is roughly 1,000 times more accurate than the old methods. If the system is heavily loaded, the difference in accuracy is larger in old methods. Facebook and Google are the customers that use this feature. Application Interface: The API to use Timed I/O is very simple. It is enabled and disabled by writing a '1' or '0' value to the sysfs enable attribute associated with the Timed I/O PPS device. Each Timed I/O pin is represented by a PPS device. When enabled, a pulse-per-second(PPS) synchronized with the system clock is continuously produced on the Timed I/O pin, otherwise it is pulled low. The Timed I/O signal on the motherboard is enabled in the BIOS setup. This patchset is dependent on [1] References: https://en.wikipedia.org/wiki/Pulse-per-second_signal https://drive.google.com/file/d/1vkBRRDuELmY8I3FlfOZaEBp-DxLW6t_V/view https://youtu.be/JLUTT-lrDqw Patch 1 adds base clock properties in clocksource structure Patch 2 adds function to convert realtime to base clock Patch 3 - 7 removes reference to convert_art_to_tsc function across drivers Patch 8 adds the pps(pulse per second) generator tio driver to the pps subsystem. Patch 9 documentation and usage of the pps tio generator module. Patch 10 includes documentation for sysfs interface. [1] https://lore.kernel.org/netdev/20231215220612.173603-2-peter.hilber@opensynergy.com/T/ Please help to review the changes. Thanks in advance, Sowjanya Lakshmi Sowjanya D (5): x86/tsc: Add base clock properties in clocksource structure timekeeping: Add function to convert realtime to base clock pps: generators: Add PPS Generator TIO Driver Documentation: driver-api: pps: Add Intel Timed I/O PPS generator ABI: pps: Add ABI documentation for Intel TIO Thomas Gleixner (5): e10002: remove convert_art_to_tsc() igc: remove convert_art_to_tsc() stmmac: intel: remove convert_art_to_tsc() ALSA: hda: remove convert_art_to_tsc() ice/ptp: remove convert_art_to_tsc() .../ABI/testing/sysfs-platform-pps-tio | 7 + Documentation/driver-api/pps.rst | 22 ++ arch/x86/include/asm/tsc.h | 3 - arch/x86/kernel/tsc.c | 94 ++----- drivers/net/ethernet/intel/e1000e/ptp.c | 3 +- drivers/net/ethernet/intel/ice/ice_ptp.c | 2 +- drivers/net/ethernet/intel/igc/igc_ptp.c | 6 +- .../net/ethernet/stmicro/stmmac/dwmac-intel.c | 3 +- drivers/pps/generators/Kconfig | 16 ++ drivers/pps/generators/Makefile | 1 + drivers/pps/generators/pps_gen_tio.c | 238 ++++++++++++++++++ include/linux/clocksource.h | 27 ++ include/linux/clocksource_ids.h | 1 + include/linux/timekeeping.h | 6 + kernel/time/timekeeping.c | 112 ++++++++- sound/pci/hda/hda_controller.c | 3 +- 16 files changed, 459 insertions(+), 85 deletions(-) create mode 100644 Documentation/ABI/testing/sysfs-platform-pps-tio create mode 100644 drivers/pps/generators/pps_gen_tio.c