Message ID | 20231207192338.400336-1-kan.liang@linux.intel.com |
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Headers |
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[2620:137:e000::3:7]) by mx.google.com with ESMTPS id e6-20020a654786000000b005c663eae379si160339pgs.269.2023.12.07.11.24.02 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 07 Dec 2023 11:24:02 -0800 (PST) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::3:7 as permitted sender) client-ip=2620:137:e000::3:7; Authentication-Results: mx.google.com; dkim=pass header.i=@intel.com header.s=Intel header.b=NBX3YbFv; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::3:7 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=intel.com Received: from out1.vger.email (depot.vger.email [IPv6:2620:137:e000::3:0]) by snail.vger.email (Postfix) with ESMTP id B60A780BC50D; Thu, 7 Dec 2023 11:24:01 -0800 (PST) X-Virus-Status: Clean X-Virus-Scanned: clamav-milter 0.103.11 at snail.vger.email Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S232865AbjLGTXw (ORCPT <rfc822;chrisfriedt@gmail.com> + 99 others); Thu, 7 Dec 2023 14:23:52 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:59086 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229472AbjLGTXv (ORCPT <rfc822;linux-kernel@vger.kernel.org>); Thu, 7 Dec 2023 14:23:51 -0500 Received: from mgamail.intel.com (mgamail.intel.com [192.55.52.88]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 6B48910EF; Thu, 7 Dec 2023 11:23:57 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1701977037; x=1733513037; h=from:to:cc:subject:date:message-id:mime-version: content-transfer-encoding; bh=Xwx4rRdSKQImronKlBDekXzVZf//CVGQYIZHr07oJ6I=; b=NBX3YbFv6CB7ezc6M1LC4XFhBLm6DV/NfnEUSVdL6bqHUjNFkMJZUbJA HC+1RZ4u2SG21EaR0UbO5y/STQJBQS2djlhloyypSLwTdf4Oh2IwE5nwd CuModD40Ipx3cFVZztlQCxp9N3Yvjybj07BtBRS3xH9NpTSVi475HZwgz 4W0ICnC33aJ34KwtD5NANlBmznAOUYAHHMfW4MfVtK1yuYiNDdpITxrww p+FQaq3oVq0CPu33GZvNknBkoANjV7lqEACThNwkyQ7vdhwTAteizb5JF S6C0I8mqBUveICRnq5rfBVXqMrDc3o1N7lOwqpsSu7cv9DrT+ltVveYo2 Q==; X-IronPort-AV: E=McAfee;i="6600,9927,10917"; a="425431716" X-IronPort-AV: E=Sophos;i="6.04,258,1695711600"; d="scan'208";a="425431716" Received: from orsmga003.jf.intel.com ([10.7.209.27]) by fmsmga101.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 07 Dec 2023 11:23:56 -0800 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6600,9927,10917"; a="721589151" X-IronPort-AV: E=Sophos;i="6.04,258,1695711600"; d="scan'208";a="721589151" Received: from kanliang-dev.jf.intel.com ([10.165.154.102]) by orsmga003.jf.intel.com with ESMTP; 07 Dec 2023 11:23:56 -0800 From: kan.liang@linux.intel.com To: acme@kernel.org, irogers@google.com, peterz@infradead.org, mingo@redhat.com, namhyung@kernel.org, jolsa@kernel.org, adrian.hunter@intel.com, john.g.garry@oracle.com, will@kernel.org, james.clark@arm.com, mike.leach@linaro.org, leo.yan@linaro.org, yuhaixin.yhx@linux.alibaba.com, renyu.zj@linux.alibaba.com, tmricht@linux.ibm.com, ravi.bangoria@amd.com, linux-kernel@vger.kernel.org, linux-perf-users@vger.kernel.org, linux-arm-kernel@lists.infradead.org Cc: Kan Liang <kan.liang@linux.intel.com> Subject: [PATCH V2 0/5] Clean up perf mem Date: Thu, 7 Dec 2023 11:23:33 -0800 Message-Id: <20231207192338.400336-1-kan.liang@linux.intel.com> X-Mailer: git-send-email 2.35.1 MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Spam-Status: No, score=-2.0 required=5.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,DKIM_VALID_EF,RCVD_IN_DNSWL_BLOCKED, RCVD_IN_MSPIKE_H3,RCVD_IN_MSPIKE_WL,SPF_HELO_NONE,SPF_NONE, T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: <linux-kernel.vger.kernel.org> X-Mailing-List: linux-kernel@vger.kernel.org X-Greylist: Sender passed SPF test, not delayed by milter-greylist-4.6.4 (snail.vger.email [0.0.0.0]); Thu, 07 Dec 2023 11:24:01 -0800 (PST) X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1784564811015540660 X-GMAIL-MSGID: 1784652279573680249 |
Series |
Clean up perf mem
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Message
Liang, Kan
Dec. 7, 2023, 7:23 p.m. UTC
From: Kan Liang <kan.liang@linux.intel.com>
Changes since V1:
- Fix strcmp of PMU name checking (Ravi)
- Fix "/," typo (Ian)
- Rename several functions with perf_pmu__mem_events prefix. (Ian)
- Fold the header removal patch into the patch where the cleanups made.
(Arnaldo)
- Add reviewed-by and tested-by from Ian and Ravi
As discussed in the below thread, the patch set is to clean up perf mem.
https://lore.kernel.org/lkml/afefab15-cffc-4345-9cf4-c6a4128d4d9c@linux.intel.com/
Introduce generic functions perf_mem_events__ptr(),
perf_mem_events__name() ,and is_mem_loads_aux_event() to replace the
ARCH specific ones.
Simplify the perf_mem_event__supported().
Only keeps the ARCH-specific perf_mem_events array in the corresponding
mem-events.c for each ARCH.
There is no functional change.
The patch set touches almost all the ARCHs, Intel, AMD, ARM, Power and
etc. But I can only test it on two Intel platforms.
Please give it try, if you have machines with other ARCHs.
Here are the test results:
Intel hybrid machine:
$perf mem record -e list
ldlat-loads : available
ldlat-stores : available
$perf mem record -e ldlat-loads -v --ldlat 50
calling: record -e cpu_atom/mem-loads,ldlat=50/P -e cpu_core/mem-loads,ldlat=50/P
$perf mem record -v
calling: record -e cpu_atom/mem-loads,ldlat=30/P -e cpu_atom/mem-stores/P -e cpu_core/mem-loads,ldlat=30/P -e cpu_core/mem-stores/P
$perf mem record -t store -v
calling: record -e cpu_atom/mem-stores/P -e cpu_core/mem-stores/P
Intel SPR:
$perf mem record -e list
ldlat-loads : available
ldlat-stores : available
$perf mem record -e ldlat-loads -v --ldlat 50
calling: record -e {cpu/mem-loads-aux/,cpu/mem-loads,ldlat=50/}:P
$perf mem record -v
calling: record -e {cpu/mem-loads-aux/,cpu/mem-loads,ldlat=30/}:P -e cpu/mem-stores/P
$perf mem record -t store -v
calling: record -e cpu/mem-stores/P
Kan Liang (5):
perf mem: Add mem_events into the supported perf_pmu
perf mem: Clean up perf_mem_events__ptr()
perf mem: Clean up perf_mem_events__name()
perf mem: Clean up perf_mem_event__supported()
perf mem: Clean up is_mem_loads_aux_event()
tools/perf/arch/arm64/util/mem-events.c | 36 +----
tools/perf/arch/arm64/util/pmu.c | 6 +
tools/perf/arch/powerpc/util/mem-events.c | 13 +-
tools/perf/arch/powerpc/util/mem-events.h | 7 +
tools/perf/arch/powerpc/util/pmu.c | 11 ++
tools/perf/arch/s390/util/pmu.c | 3 +
tools/perf/arch/x86/util/mem-events.c | 99 ++----------
tools/perf/arch/x86/util/pmu.c | 11 ++
tools/perf/builtin-c2c.c | 28 +++-
tools/perf/builtin-mem.c | 28 +++-
tools/perf/util/mem-events.c | 181 +++++++++++++---------
tools/perf/util/mem-events.h | 15 +-
tools/perf/util/pmu.c | 4 +-
tools/perf/util/pmu.h | 7 +
14 files changed, 233 insertions(+), 216 deletions(-)
create mode 100644 tools/perf/arch/powerpc/util/mem-events.h
create mode 100644 tools/perf/arch/powerpc/util/pmu.c
Comments
Em Thu, Dec 07, 2023 at 11:23:33AM -0800, kan.liang@linux.intel.com escreveu: > From: Kan Liang <kan.liang@linux.intel.com> > > Changes since V1: > - Fix strcmp of PMU name checking (Ravi) > - Fix "/," typo (Ian) > - Rename several functions with perf_pmu__mem_events prefix. (Ian) > - Fold the header removal patch into the patch where the cleanups made. > (Arnaldo) > - Add reviewed-by and tested-by from Ian and Ravi It would be good to have a Tested-by from people working in all the architectures affectes, like we got from Ravi for AMD, can we get those? I'm applying it locally for test building, will push to perf-tools-next/tmp.perf-tools-next for a while, so there is some time to test. ARM64 (Leo?) and ppc, for PPC... humm Ravi did it, who could test it now? - Arnaldo > As discussed in the below thread, the patch set is to clean up perf mem. > https://lore.kernel.org/lkml/afefab15-cffc-4345-9cf4-c6a4128d4d9c@linux.intel.com/ > > Introduce generic functions perf_mem_events__ptr(), > perf_mem_events__name() ,and is_mem_loads_aux_event() to replace the > ARCH specific ones. > Simplify the perf_mem_event__supported(). > > Only keeps the ARCH-specific perf_mem_events array in the corresponding > mem-events.c for each ARCH. > > There is no functional change. > > The patch set touches almost all the ARCHs, Intel, AMD, ARM, Power and > etc. But I can only test it on two Intel platforms. > Please give it try, if you have machines with other ARCHs. > > Here are the test results: > Intel hybrid machine: > > $perf mem record -e list > ldlat-loads : available > ldlat-stores : available > > $perf mem record -e ldlat-loads -v --ldlat 50 > calling: record -e cpu_atom/mem-loads,ldlat=50/P -e cpu_core/mem-loads,ldlat=50/P > > $perf mem record -v > calling: record -e cpu_atom/mem-loads,ldlat=30/P -e cpu_atom/mem-stores/P -e cpu_core/mem-loads,ldlat=30/P -e cpu_core/mem-stores/P > > $perf mem record -t store -v > calling: record -e cpu_atom/mem-stores/P -e cpu_core/mem-stores/P > > > Intel SPR: > $perf mem record -e list > ldlat-loads : available > ldlat-stores : available > > $perf mem record -e ldlat-loads -v --ldlat 50 > calling: record -e {cpu/mem-loads-aux/,cpu/mem-loads,ldlat=50/}:P > > $perf mem record -v > calling: record -e {cpu/mem-loads-aux/,cpu/mem-loads,ldlat=30/}:P -e cpu/mem-stores/P > > $perf mem record -t store -v > calling: record -e cpu/mem-stores/P > > Kan Liang (5): > perf mem: Add mem_events into the supported perf_pmu > perf mem: Clean up perf_mem_events__ptr() > perf mem: Clean up perf_mem_events__name() > perf mem: Clean up perf_mem_event__supported() > perf mem: Clean up is_mem_loads_aux_event() > > tools/perf/arch/arm64/util/mem-events.c | 36 +---- > tools/perf/arch/arm64/util/pmu.c | 6 + > tools/perf/arch/powerpc/util/mem-events.c | 13 +- > tools/perf/arch/powerpc/util/mem-events.h | 7 + > tools/perf/arch/powerpc/util/pmu.c | 11 ++ > tools/perf/arch/s390/util/pmu.c | 3 + > tools/perf/arch/x86/util/mem-events.c | 99 ++---------- > tools/perf/arch/x86/util/pmu.c | 11 ++ > tools/perf/builtin-c2c.c | 28 +++- > tools/perf/builtin-mem.c | 28 +++- > tools/perf/util/mem-events.c | 181 +++++++++++++--------- > tools/perf/util/mem-events.h | 15 +- > tools/perf/util/pmu.c | 4 +- > tools/perf/util/pmu.h | 7 + > 14 files changed, 233 insertions(+), 216 deletions(-) > create mode 100644 tools/perf/arch/powerpc/util/mem-events.h > create mode 100644 tools/perf/arch/powerpc/util/pmu.c > > -- > 2.35.1 >
> On 08-Dec-2023, at 2:01 AM, Arnaldo Carvalho de Melo <acme@kernel.org> wrote: > > Em Thu, Dec 07, 2023 at 11:23:33AM -0800, kan.liang@linux.intel.com escreveu: >> From: Kan Liang <kan.liang@linux.intel.com> >> >> Changes since V1: >> - Fix strcmp of PMU name checking (Ravi) >> - Fix "/," typo (Ian) >> - Rename several functions with perf_pmu__mem_events prefix. (Ian) >> - Fold the header removal patch into the patch where the cleanups made. >> (Arnaldo) >> - Add reviewed-by and tested-by from Ian and Ravi > > It would be good to have a Tested-by from people working in all the > architectures affectes, like we got from Ravi for AMD, can we get those? > > I'm applying it locally for test building, will push to > perf-tools-next/tmp.perf-tools-next for a while, so there is some time > to test. > > ARM64 (Leo?) and ppc, for PPC... humm Ravi did it, who could test it now? Hi Arnaldo, Ravi Looking into this for testing on powerpc. Will update back. Thanks Athira > > - Arnaldo > >> As discussed in the below thread, the patch set is to clean up perf mem. >> https://lore.kernel.org/lkml/afefab15-cffc-4345-9cf4-c6a4128d4d9c@linux.intel.com/ >> >> Introduce generic functions perf_mem_events__ptr(), >> perf_mem_events__name() ,and is_mem_loads_aux_event() to replace the >> ARCH specific ones. >> Simplify the perf_mem_event__supported(). >> >> Only keeps the ARCH-specific perf_mem_events array in the corresponding >> mem-events.c for each ARCH. >> >> There is no functional change. >> >> The patch set touches almost all the ARCHs, Intel, AMD, ARM, Power and >> etc. But I can only test it on two Intel platforms. >> Please give it try, if you have machines with other ARCHs. >> >> Here are the test results: >> Intel hybrid machine: >> >> $perf mem record -e list >> ldlat-loads : available >> ldlat-stores : available >> >> $perf mem record -e ldlat-loads -v --ldlat 50 >> calling: record -e cpu_atom/mem-loads,ldlat=50/P -e cpu_core/mem-loads,ldlat=50/P >> >> $perf mem record -v >> calling: record -e cpu_atom/mem-loads,ldlat=30/P -e cpu_atom/mem-stores/P -e cpu_core/mem-loads,ldlat=30/P -e cpu_core/mem-stores/P >> >> $perf mem record -t store -v >> calling: record -e cpu_atom/mem-stores/P -e cpu_core/mem-stores/P >> >> >> Intel SPR: >> $perf mem record -e list >> ldlat-loads : available >> ldlat-stores : available >> >> $perf mem record -e ldlat-loads -v --ldlat 50 >> calling: record -e {cpu/mem-loads-aux/,cpu/mem-loads,ldlat=50/}:P >> >> $perf mem record -v >> calling: record -e {cpu/mem-loads-aux/,cpu/mem-loads,ldlat=30/}:P -e cpu/mem-stores/P >> >> $perf mem record -t store -v >> calling: record -e cpu/mem-stores/P >> >> Kan Liang (5): >> perf mem: Add mem_events into the supported perf_pmu >> perf mem: Clean up perf_mem_events__ptr() >> perf mem: Clean up perf_mem_events__name() >> perf mem: Clean up perf_mem_event__supported() >> perf mem: Clean up is_mem_loads_aux_event() >> >> tools/perf/arch/arm64/util/mem-events.c | 36 +---- >> tools/perf/arch/arm64/util/pmu.c | 6 + >> tools/perf/arch/powerpc/util/mem-events.c | 13 +- >> tools/perf/arch/powerpc/util/mem-events.h | 7 + >> tools/perf/arch/powerpc/util/pmu.c | 11 ++ >> tools/perf/arch/s390/util/pmu.c | 3 + >> tools/perf/arch/x86/util/mem-events.c | 99 ++---------- >> tools/perf/arch/x86/util/pmu.c | 11 ++ >> tools/perf/builtin-c2c.c | 28 +++- >> tools/perf/builtin-mem.c | 28 +++- >> tools/perf/util/mem-events.c | 181 +++++++++++++--------- >> tools/perf/util/mem-events.h | 15 +- >> tools/perf/util/pmu.c | 4 +- >> tools/perf/util/pmu.h | 7 + >> 14 files changed, 233 insertions(+), 216 deletions(-) >> create mode 100644 tools/perf/arch/powerpc/util/mem-events.h >> create mode 100644 tools/perf/arch/powerpc/util/pmu.c >> >> -- >> 2.35.1 >> > > -- > > - Arnaldo
On 2023-12-13 4:51 a.m., Athira Rajeev wrote: > > >> On 08-Dec-2023, at 2:01 AM, Arnaldo Carvalho de Melo <acme@kernel.org> wrote: >> >> Em Thu, Dec 07, 2023 at 11:23:33AM -0800, kan.liang@linux.intel.com escreveu: >>> From: Kan Liang <kan.liang@linux.intel.com> >>> >>> Changes since V1: >>> - Fix strcmp of PMU name checking (Ravi) >>> - Fix "/," typo (Ian) >>> - Rename several functions with perf_pmu__mem_events prefix. (Ian) >>> - Fold the header removal patch into the patch where the cleanups made. >>> (Arnaldo) >>> - Add reviewed-by and tested-by from Ian and Ravi >> >> It would be good to have a Tested-by from people working in all the >> architectures affectes, like we got from Ravi for AMD, can we get those? >> >> I'm applying it locally for test building, will push to >> perf-tools-next/tmp.perf-tools-next for a while, so there is some time >> to test. >> >> ARM64 (Leo?) and ppc, for PPC... humm Ravi did it, who could test it now? > Hi Arnaldo, Ravi > > Looking into this for testing on powerpc. Will update back. > Thanks Athira. I've sent out the latest V3. Please give it a try. https://lore.kernel.org/lkml/20231213195154.1085945-1-kan.liang@linux.intel.com/ Thanks, Kan > Thanks > Athira >> >> - Arnaldo >> >>> As discussed in the below thread, the patch set is to clean up perf mem. >>> https://lore.kernel.org/lkml/afefab15-cffc-4345-9cf4-c6a4128d4d9c@linux.intel.com/ >>> >>> Introduce generic functions perf_mem_events__ptr(), >>> perf_mem_events__name() ,and is_mem_loads_aux_event() to replace the >>> ARCH specific ones. >>> Simplify the perf_mem_event__supported(). >>> >>> Only keeps the ARCH-specific perf_mem_events array in the corresponding >>> mem-events.c for each ARCH. >>> >>> There is no functional change. >>> >>> The patch set touches almost all the ARCHs, Intel, AMD, ARM, Power and >>> etc. But I can only test it on two Intel platforms. >>> Please give it try, if you have machines with other ARCHs. >>> >>> Here are the test results: >>> Intel hybrid machine: >>> >>> $perf mem record -e list >>> ldlat-loads : available >>> ldlat-stores : available >>> >>> $perf mem record -e ldlat-loads -v --ldlat 50 >>> calling: record -e cpu_atom/mem-loads,ldlat=50/P -e cpu_core/mem-loads,ldlat=50/P >>> >>> $perf mem record -v >>> calling: record -e cpu_atom/mem-loads,ldlat=30/P -e cpu_atom/mem-stores/P -e cpu_core/mem-loads,ldlat=30/P -e cpu_core/mem-stores/P >>> >>> $perf mem record -t store -v >>> calling: record -e cpu_atom/mem-stores/P -e cpu_core/mem-stores/P >>> >>> >>> Intel SPR: >>> $perf mem record -e list >>> ldlat-loads : available >>> ldlat-stores : available >>> >>> $perf mem record -e ldlat-loads -v --ldlat 50 >>> calling: record -e {cpu/mem-loads-aux/,cpu/mem-loads,ldlat=50/}:P >>> >>> $perf mem record -v >>> calling: record -e {cpu/mem-loads-aux/,cpu/mem-loads,ldlat=30/}:P -e cpu/mem-stores/P >>> >>> $perf mem record -t store -v >>> calling: record -e cpu/mem-stores/P >>> >>> Kan Liang (5): >>> perf mem: Add mem_events into the supported perf_pmu >>> perf mem: Clean up perf_mem_events__ptr() >>> perf mem: Clean up perf_mem_events__name() >>> perf mem: Clean up perf_mem_event__supported() >>> perf mem: Clean up is_mem_loads_aux_event() >>> >>> tools/perf/arch/arm64/util/mem-events.c | 36 +---- >>> tools/perf/arch/arm64/util/pmu.c | 6 + >>> tools/perf/arch/powerpc/util/mem-events.c | 13 +- >>> tools/perf/arch/powerpc/util/mem-events.h | 7 + >>> tools/perf/arch/powerpc/util/pmu.c | 11 ++ >>> tools/perf/arch/s390/util/pmu.c | 3 + >>> tools/perf/arch/x86/util/mem-events.c | 99 ++---------- >>> tools/perf/arch/x86/util/pmu.c | 11 ++ >>> tools/perf/builtin-c2c.c | 28 +++- >>> tools/perf/builtin-mem.c | 28 +++- >>> tools/perf/util/mem-events.c | 181 +++++++++++++--------- >>> tools/perf/util/mem-events.h | 15 +- >>> tools/perf/util/pmu.c | 4 +- >>> tools/perf/util/pmu.h | 7 + >>> 14 files changed, 233 insertions(+), 216 deletions(-) >>> create mode 100644 tools/perf/arch/powerpc/util/mem-events.h >>> create mode 100644 tools/perf/arch/powerpc/util/pmu.c >>> >>> -- >>> 2.35.1 >>> >> >> -- >> >> - Arnaldo > > >