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[23.128.96.31]) by mx.google.com with ESMTPS id u2-20020a63d342000000b005b8f24e6526si12351929pgi.234.2023.11.28.08.49.35 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 28 Nov 2023 08:49:36 -0800 (PST) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 23.128.96.31 as permitted sender) client-ip=23.128.96.31; Authentication-Results: mx.google.com; dkim=pass header.i=@foss.st.com header.s=selector1 header.b="7t+x/6KG"; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 23.128.96.31 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=foss.st.com Received: from out1.vger.email (depot.vger.email [IPv6:2620:137:e000::3:0]) by morse.vger.email (Postfix) with ESMTP id E5737806943C; Tue, 28 Nov 2023 08:49:33 -0800 (PST) X-Virus-Status: Clean X-Virus-Scanned: clamav-milter 0.103.11 at morse.vger.email Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1344670AbjK1QtZ (ORCPT + 99 others); Tue, 28 Nov 2023 11:49:25 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:33814 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229671AbjK1QtY (ORCPT ); Tue, 28 Nov 2023 11:49:24 -0500 Received: from mx07-00178001.pphosted.com (mx07-00178001.pphosted.com [185.132.182.106]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 7838AD4B; Tue, 28 Nov 2023 08:49:30 -0800 (PST) Received: from pps.filterd (m0369458.ppops.net [127.0.0.1]) by mx07-00178001.pphosted.com (8.17.1.22/8.17.1.22) with ESMTP id 3ASEY25D012922; Tue, 28 Nov 2023 17:49:07 +0100 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=foss.st.com; h= from:to:cc:subject:date:message-id:mime-version :content-transfer-encoding:content-type; s=selector1; bh=iB8QxrE lAv61BdkbTURf/4YgreurgxTFFxpS69+3uGo=; b=7t+x/6KGi240X0k541eunHF Gl9QJCuAwAIAYxYUi5WTQBVW9QOQJQ7xjA/QlihkN7/8+qE0Gi4fHKYkCjZK47IK 1UGop2m+qX4a+IRaAsvTAOK57CFg6v/0l83b2R4piVV4TKA6FkdGvWhoiXCWtW67 2NhpeWQQxjvdeF4mbVOChPN1k4IUmMHv9ILtBkkzbgc5iDIIdAi57GhJ1UD8tYJk ELeQGAcLJB6obvv37D5LzeW70kz1h7HyAk+LWsUZGlYjAc1wmSUAMvD7Krdfaizg aghsLtlH8rb1CLy2hiLwKmaSP7RyEXNw3lZ5NU3+TG+NeBGJSspIV3gRSYK9/wA= = Received: from beta.dmz-eu.st.com (beta.dmz-eu.st.com [164.129.1.35]) by mx07-00178001.pphosted.com (PPS) with ESMTPS id 3ums0rpgwh-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Tue, 28 Nov 2023 17:49:07 +0100 (CET) Received: from euls16034.sgp.st.com (euls16034.sgp.st.com [10.75.44.20]) by beta.dmz-eu.st.com (STMicroelectronics) with ESMTP id 3703F10002A; Tue, 28 Nov 2023 17:49:06 +0100 (CET) Received: from Webmail-eu.st.com (shfdag1node1.st.com [10.75.129.69]) by euls16034.sgp.st.com (STMicroelectronics) with ESMTP id 2DB1926028A; Tue, 28 Nov 2023 17:49:06 +0100 (CET) Received: from localhost (10.201.21.240) by SHFDAG1NODE1.st.com (10.75.129.69) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.27; Tue, 28 Nov 2023 17:49:05 +0100 From: To: Michael Turquette , Stephen Boyd , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Maxime Coquelin , Alexandre Torgue , Philipp Zabel , Gabriel Fernandez CC: , , , , Subject: [PATCH v4 0/5] Introduce STM32MP257 clock driver Date: Tue, 28 Nov 2023 17:48:46 +0100 Message-ID: <20231128164851.588315-1-gabriel.fernandez@foss.st.com> X-Mailer: git-send-email 2.25.1 MIME-Version: 1.0 X-Originating-IP: [10.201.21.240] X-ClientProxiedBy: EQNCAS1NODE4.st.com (10.75.129.82) To SHFDAG1NODE1.st.com (10.75.129.69) X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.272,Aquarius:18.0.997,Hydra:6.0.619,FMLib:17.11.176.26 definitions=2023-11-28_18,2023-11-27_01,2023-05-22_02 X-Spam-Status: No, score=-0.9 required=5.0 tests=DKIM_SIGNED,DKIM_VALID, DKIM_VALID_AU,HEADER_FROM_DIFFERENT_DOMAINS,MAILING_LIST_MULTI, SPF_HELO_NONE,SPF_PASS,T_SCC_BODY_TEXT_LINE autolearn=unavailable autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on morse.vger.email Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-Greylist: Sender passed SPF test, not delayed by milter-greylist-4.6.4 (morse.vger.email [0.0.0.0]); Tue, 28 Nov 2023 08:49:34 -0800 (PST) X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1783827190086961202 X-GMAIL-MSGID: 1783827190086961202 From: Gabriel Fernandez This patch-set introduces clock driver for STM32MP257 based on Arm Cortex-35. It creates also a menuconfig for all STM32MP clock drivers. The STM32MP1 and STM32MP13 are now in same stm32 directory v4: - use GPL-2.0-only OR BSD-2-Clause for clock and reset binding files - use quotes ' for #clock-cells and #reset-cells in YAML documentation - reset binding start now to 0 instead 1 - improve management of reset lines that are not managed v3: - from Rob Herring change clock item description in YAML documentation v2: - rework reset binding (use ID witch start from 0) - rework reset driver to manage STM32MP13 / STM32MP15 / STM32MP25 - rework YAML documentation Gabriel Fernandez (5): clk: stm32mp1: move stm32mp1 clock driver into stm32 directory clk: stm32mp1: use stm32mp13 reset driver dt-bindings: stm32: add clocks and reset binding for stm32mp25 platform clk: stm32: introduce clocks for STM32MP257 platform arm64: dts: st: add rcc support in stm32mp251 .../bindings/clock/st,stm32mp25-rcc.yaml | 76 + arch/arm64/boot/dts/st/stm32mp251.dtsi | 59 +- drivers/clk/Kconfig | 11 +- drivers/clk/Makefile | 1 - drivers/clk/stm32/Kconfig | 36 + drivers/clk/stm32/Makefile | 2 + drivers/clk/stm32/clk-stm32-core.c | 5 +- drivers/clk/stm32/clk-stm32-core.h | 5 +- drivers/clk/{ => stm32}/clk-stm32mp1.c | 127 +- drivers/clk/stm32/clk-stm32mp13.c | 9 +- drivers/clk/stm32/clk-stm32mp25.c | 1125 ++++ drivers/clk/stm32/reset-stm32.c | 73 +- drivers/clk/stm32/reset-stm32.h | 15 +- drivers/clk/stm32/stm32mp25_rcc.h | 4977 +++++++++++++++++ include/dt-bindings/clock/st,stm32mp25-rcc.h | 492 ++ include/dt-bindings/reset/st,stm32mp25-rcc.h | 167 + 16 files changed, 6999 insertions(+), 181 deletions(-) create mode 100644 Documentation/devicetree/bindings/clock/st,stm32mp25-rcc.yaml create mode 100644 drivers/clk/stm32/Kconfig rename drivers/clk/{ => stm32}/clk-stm32mp1.c (95%) create mode 100644 drivers/clk/stm32/clk-stm32mp25.c create mode 100644 drivers/clk/stm32/stm32mp25_rcc.h create mode 100644 include/dt-bindings/clock/st,stm32mp25-rcc.h create mode 100644 include/dt-bindings/reset/st,stm32mp25-rcc.h