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Mon, 27 Nov 2023 12:14:23 +0000 Received: from nalasex01a.na.qualcomm.com (nalasex01a.na.qualcomm.com [10.47.209.196]) by NALASPPMTA03.qualcomm.com (8.17.1.5/8.17.1.5) with ESMTPS id 3ARCEMCD014861 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Mon, 27 Nov 2023 12:14:22 GMT Received: from hu-krichai-hyd.qualcomm.com (10.80.80.8) by nalasex01a.na.qualcomm.com (10.47.209.196) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1118.40; Mon, 27 Nov 2023 04:14:16 -0800 From: Krishna chaitanya chundru Subject: [PATCH v3 0/3] phy: qcom-qmp-pcie: Add support to keep refclk always on Date: Mon, 27 Nov 2023 17:43:48 +0530 Message-ID: <20231127-refclk_always_on-v3-0-26d969fa8f1d@quicinc.com> MIME-Version: 1.0 X-B4-Tracking: v=1; b=H4sIAP6HZGUC/33NwQ6CMAyA4VchOzvDOmXgyfcwhmxjSCNuuumUE N7dwUkT4/Fv2q8jCcajCWSXjcSbiAGdTcFXGdGdtCdDsUlNIAfOWF5Qb1rdn2vZP+UQamdppYw 0JVRCq5Kks2vawNdCHo6pOwx354flQ2Tz9A8WGc0pE1K0Tam2HNT+9kCNVq+1u5CZi/BJiB8EJ KIxwKsCWr1R/JuYpukNo4RcpvUAAAA= To: Andy Gross , Bjorn Andersson , Konrad Dybcio , Vinod Koul , Kishon Vijay Abraham I , Rob Herring , Krzysztof Kozlowski , Conor Dooley CC: , , , , , , , , , , "Krishna chaitanya chundru" , Dmitry Baryshkov X-Mailer: b4 0.13-dev-83828 X-Developer-Signature: v=1; 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Mon, 27 Nov 2023 04:14:41 -0800 (PST) X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1783719301010813844 X-GMAIL-MSGID: 1783719301010813844 This series adds support to provide refclk to endpoint even in low power states. Due to some platform specific issues with CLKREQ signal, it is not being propagated to the host and as host doesn't know the clkreq signal host is not sending refclk. Due to this endpoint is seeing linkdown and going to bad state. To avoid those ref clk should be provided always to the endpoint. The issue is coming only when ep intiates the L1.1 or L1.2 exit and clkreq is not being propagated properly to the host. Signed-off-by: Krishna chaitanya chundru --- Changes in v3: - Updated the dt-binding description as suggested by Dmitry. - Added the new macros for v5_20 and v6_20 as suggested by Dmitry. - Link to v2: https://lore.kernel.org/r/20231107-refclk_always_on-v2-0-de23962fc4b3@quicinc.com Changes in v2: - Added refclk cntrl registers to the applicable phy versions & added reg layout where - refclk cntrl offset needs to be updated (Dmitry) - Error out if refclk_always_on is set and there is no refclk control register to enable it (Dmitry) - updated the dt-binding description & some nit's as suggested by (Bjorn) - Link to v1: https://lore.kernel.org/r/20231106-refclk_always_on-v1-0-17a7fd8b532b@quicinc.com --- Krishna chaitanya chundru (3): dt-bindings: phy: qcom,qmp: Add PCIe qcom,refclk-always-on property phy: qcom-qmp-pcie: Add endpoint refclk control register offset phy: qcom-qmp-pcie: Add support for keeping refclk always on .../bindings/phy/qcom,sc8280xp-qmp-pcie-phy.yaml | 7 ++++ drivers/phy/qualcomm/phy-qcom-qmp-pcie.c | 40 ++++++++++++++++++++-- drivers/phy/qualcomm/phy-qcom-qmp-pcs-pcie-v5.h | 1 + drivers/phy/qualcomm/phy-qcom-qmp-pcs-pcie-v5_20.h | 1 + drivers/phy/qualcomm/phy-qcom-qmp-pcs-pcie-v6_20.h | 1 + drivers/phy/qualcomm/phy-qcom-qmp-pcs-v5_20.h | 4 +++ drivers/phy/qualcomm/phy-qcom-qmp-pcs-v6_20.h | 4 +++ 7 files changed, 55 insertions(+), 3 deletions(-) --- base-commit: 71e68e182e382e951d6248bccc3c960dcec5a718 change-id: 20231106-refclk_always_on-9beae8297cb8 Best regards,