mbox series

[v3,0/9] irqchip/renesas-rzg2l: add support for RZ/G3S SoC

Message ID 20231120111820.87398-1-claudiu.beznea.uj@bp.renesas.com
Headers
Series irqchip/renesas-rzg2l: add support for RZ/G3S SoC |

Message

claudiu beznea Nov. 20, 2023, 11:18 a.m. UTC 
  From: Claudiu Beznea <claudiu.beznea.uj@bp.renesas.com>

Hi,

Series adds support for IA55 available on RZ/G3S SoC.
Patches are split as follows:
- 1/9 adds IA55 clock
- 2-4/9 minor cleanups to align with the suggestions at [1] and
  coding style recommendations
- 5/9 implement restriction described in HW manual for ISCR register
- 6/9 add a macro to retrieve TITSR base address based on it's index
- 7/9 add suspend to RAM support
- 8/9 updates documentation
- 9/9 adds IA55 device tree node

Thank you,
Claudiu Beznea

[1] https://www.kernel.org/doc/html/latest/process/maintainer-tip.html#struct-declarations-and-initializers

Changes in v3:
- kept driver private data object as pointer
- moved patch 1/9 from v2 (dt-bindings: interrupt-controller: renesas,rzg2l-irqc: Document RZ/G3S)
  after IRQ controller driver feature patches

Changes in v2:
- collected Conor's tag
- updated commit description according to code review comments
- added patches 4, 5 according to review recommendations
- updated patch 7/9 to retrieve only TITSR base address; dropped the rest
  of the changes for the moment
- in patch 8/9 use local variable in suspend/resume functions for controller's
  base address, indent initialized structures members to tabs, updated
  private driver data structure name
- patch 3/7 from v1 was replaced by patch 7/9 in v2
- patch 5/7 from v1 was renamed "Add support for suspend to RAM"
- cleanup patches were kept at the beginning of the series and features at the end

Claudiu Beznea (9):
  clk: renesas: r9a08g045: Add IA55 pclk and its reset
  irqchip/renesas-rzg2l: Use tabs instead of spaces
  irqchip/renesas-rzg2l: Align struct member names to tabs
  irqchip/renesas-rzg2l: Document structure members
  irqchip/renesas-rzg2l: Implement restriction when writing ISCR
    register
  irqchip/renesas-rzg2l: Add macro to retrieve TITSR register offset
    based on register's index
  irqchip/renesas-rzg2l: Add support for suspend to RAM
  dt-bindings: interrupt-controller: renesas,rzg2l-irqc: Document RZ/G3S
  arm64: dts: renesas: r9108g045: Add IA55 interrupt controller node

 .../renesas,rzg2l-irqc.yaml                   |   5 +-
 arch/arm64/boot/dts/renesas/r9a08g045.dtsi    |  68 +++++++++++
 drivers/clk/renesas/r9a08g045-cpg.c           |   3 +
 drivers/irqchip/irq-renesas-rzg2l.c           | 110 +++++++++++++-----
 4 files changed, 158 insertions(+), 28 deletions(-)

Comments

Geert Uytterhoeven Dec. 13, 2023, 2:11 p.m. UTC | #1 
On Tue, Nov 21, 2023 at 10:59 AM Geert Uytterhoeven
<geert@linux-m68k.org> wrote:
> On Mon, 20 Nov 2023, Claudiu wrote:
> > From: Claudiu Beznea <claudiu.beznea.uj@bp.renesas.com>
> >
> > IA55 interrupt controller is available on RZ/G3S SoC. Add IA55 pclk and
> > its reset.
> >
> > Signed-off-by: Claudiu Beznea <claudiu.beznea.uj@bp.renesas.com>
>
> Thanks for your patch!
>
> > --- a/drivers/clk/renesas/r9a08g045-cpg.c
> > +++ b/drivers/clk/renesas/r9a08g045-cpg.c
> > @@ -188,6 +188,7 @@ static const struct cpg_core_clk r9a08g045_core_clks[] __initconst = {
> >
> > static const struct rzg2l_mod_clk r9a08g045_mod_clks[] = {
> >       DEF_MOD("gic_gicclk",           R9A08G045_GIC600_GICCLK, R9A08G045_CLK_P1, 0x514, 0),
> > +     DEF_MOD("ia55_pclk",            R9A08G045_IA55_PCLK, R9A08G045_CLK_P2, 0x518, 0),
>
> This conflicts with [1], which you sent just before.
>
> If that patch goes in first, I guess this new entry should gain
> ", MSTOP(PERI_CPU, BIT(13))", just like the entry for ia55_clk?
>
> >       DEF_MOD("ia55_clk",             R9A08G045_IA55_CLK, R9A08G045_CLK_P1, 0x518, 1),
> >       DEF_MOD("dmac_aclk",            R9A08G045_DMAC_ACLK, R9A08G045_CLK_P3, 0x52c, 0),
> >       DEF_MOD("sdhi0_imclk",          R9A08G045_SDHI0_IMCLK, CLK_SD0_DIV4, 0x554, 0),
>
> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
>
> [1] "clk: renesas: rzg2l-cpg: Add support for MSTOP"
>      https://lore.kernel.org/r/20231120070024.4079344-4-claudiu.beznea.uj@bp.renesas.com

As the MSTOP support is on hold, I will queue this in renesas-clk-for-v6.8.

Gr{oetje,eeting}s,

                        Geert
Geert Uytterhoeven Dec. 13, 2023, 2:18 p.m. UTC | #2 
On Wed, Nov 22, 2023 at 7:16 AM Claudiu <claudiu.beznea@tuxon.dev> wrote:
> From: Claudiu Beznea <claudiu.beznea.uj@bp.renesas.com>
>
> Add IA55 interrupt controller node and set it as interrupt parent for pin
> controller.
>
> Signed-off-by: Claudiu Beznea <claudiu.beznea.uj@bp.renesas.com>

Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
i.e. will queue in renesas-devel for v6.8.

Gr{oetje,eeting}s,

                        Geert