Message ID | 20231120084606.4083194-1-claudiu.beznea.uj@bp.renesas.com |
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([82.78.167.183]) by smtp.gmail.com with ESMTPSA id b8-20020a5d45c8000000b003142e438e8csm10435267wrs.26.2023.11.20.00.46.14 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 20 Nov 2023 00:46:16 -0800 (PST) From: Claudiu <claudiu.beznea@tuxon.dev> X-Google-Original-From: Claudiu <claudiu.beznea.uj@bp.renesas.com> To: s.shtylyov@omp.ru, davem@davemloft.net, edumazet@google.com, kuba@kernel.org, pabeni@redhat.com, p.zabel@pengutronix.de, yoshihiro.shimoda.uh@renesas.com, geert+renesas@glider.be, wsa+renesas@sang-engineering.com, biju.das.jz@bp.renesas.com, prabhakar.mahadev-lad.rj@bp.renesas.com, sergei.shtylyov@cogentembedded.com, mitsuhiro.kimura.kc@renesas.com, masaru.nagai.vx@renesas.com Cc: netdev@vger.kernel.org, linux-renesas-soc@vger.kernel.org, linux-kernel@vger.kernel.org, Claudiu Beznea <claudiu.beznea.uj@bp.renesas.com> Subject: [PATCH 00/13] net: ravb: Add suspend to RAM and runtime PM support for RZ/G3S Date: Mon, 20 Nov 2023 10:45:53 +0200 Message-Id: <20231120084606.4083194-1-claudiu.beznea.uj@bp.renesas.com> X-Mailer: git-send-email 2.39.2 MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit X-Spam-Status: No, score=-2.1 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,RCVD_IN_DNSWL_NONE, SPF_HELO_NONE,SPF_PASS,T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: <linux-kernel.vger.kernel.org> X-Mailing-List: linux-kernel@vger.kernel.org X-Greylist: Sender passed SPF test, not delayed by milter-greylist-4.6.4 (snail.vger.email [0.0.0.0]); Mon, 20 Nov 2023 00:46:39 -0800 (PST) X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1783117505708697022 X-GMAIL-MSGID: 1783424965244219427 |
Series |
net: ravb: Add suspend to RAM and runtime PM support for RZ/G3S
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Message
claudiu beznea
Nov. 20, 2023, 8:45 a.m. UTC
From: Claudiu Beznea <claudiu.beznea.uj@bp.renesas.com>
Hi,
This series adds suspend to RAM and runtime PM support for Ethernet
IP available on RZ/G3S (R9A08G045) SoC.
Along with it series contains preparatory fixes and cleanups.
Thank you,
Claudiu Beznea
Claudiu Beznea (13):
net: ravb: Check return value of reset_control_deassert()
net: ravb: Use pm_runtime_resume_and_get()
net: ravb: Make write access to CXR35 first before accessing other
EMAC registers
net: ravb: Start TX queues after HW initialization succeeded
net: ravb: Stop DMA in case of failures on ravb_open()
net: ravb: Let IP specific receive function to interrogate descriptors
net: ravb: Rely on PM domain to enable gptp_clk
net: ravb: Rely on PM domain to enable refclk
net: ravb: Make reset controller support mandatory
net: ravb: Switch to SYSTEM_SLEEP_PM_OPS()/RUNTIME_PM_OPS() and
pm_ptr()
net: ravb: Use tabs instead of spaces
net: ravb: Assert/deassert reset on suspend/resume
net: ravb: Add runtime PM support
drivers/net/ethernet/renesas/ravb.h | 2 +
drivers/net/ethernet/renesas/ravb_main.c | 220 ++++++++++++++++-------
2 files changed, 160 insertions(+), 62 deletions(-)
Comments
On 20.11.2023 21:44, Sergey Shtylyov wrote: > On 11/20/23 11:45 AM, Claudiu wrote: > >> From: Claudiu Beznea <claudiu.beznea.uj@bp.renesas.com> >> >> Hardware manual of RZ/G3S (and RZ/G2L) specifies the following on the >> description of CXR35 register (chapter "PHY interface select register >> (CXR35)"): "After release reset, make write-access to this register before >> making write-access to other registers (except MDIOMOD). Even if not need >> to change the value of this register, make write-access to this register >> at least one time. Because RGMII/MII MODE is recognized by accessing this >> register". >> >> The setup procedure for EMAC module (chapter "Setup procedure" of RZ/G3S, >> RZ/G2L manuals) specifies the E-MAC.CXR35 register is the first EMAC >> register that is to be configured. >> >> Note [A] from chapter "PHY interface select register (CXR35)" specifies >> the following: >> [A] The case which CXR35 SEL_XMII is used for the selection of RGMII/MII >> in APB Clock 100 MHz. >> (1) To use RGMII interface, Set ‘H’03E8_0000’ to this register. >> (2) To use MII interface, Set ‘H’03E8_0002’ to this register. >> >> Take into account these indication. >> >> Fixes: 1089877ada8d ("ravb: Add RZ/G2L MII interface support") > > The bug fixes should be submitted separately and against the net.git repo... OK, thanks for pointing it. > >> Signed-off-by: Claudiu Beznea <claudiu.beznea.uj@bp.renesas.com> > > Reviewed-by: Sergey Shtylyov <s.shtylyov@omp.ru> > > [...] > > MBR, Sergey
On 11/21/23 8:59 AM, claudiu beznea wrote: [...] >>> From: Claudiu Beznea <claudiu.beznea.uj@bp.renesas.com> >>> >>> reset_control_deassert() could return an error. Some devices cannot work >>> if reset signal de-assert operation fails. To avoid this check the return >>> code of reset_control_deassert() in ravb_probe() and take proper action. >>> >>> Fixes: 0d13a1a464a0 ("ravb: Add reset support") >>> Signed-off-by: Claudiu Beznea <claudiu.beznea.uj@bp.renesas.com> >>> --- >>> drivers/net/ethernet/renesas/ravb_main.c | 7 ++++++- >>> 1 file changed, 6 insertions(+), 1 deletion(-) >>> >>> diff --git a/drivers/net/ethernet/renesas/ravb_main.c b/drivers/net/ethernet/renesas/ravb_main.c >>> index c70cff80cc99..342978bdbd7e 100644 >>> --- a/drivers/net/ethernet/renesas/ravb_main.c >>> +++ b/drivers/net/ethernet/renesas/ravb_main.c >>> @@ -2645,7 +2645,12 @@ static int ravb_probe(struct platform_device *pdev) >>> ndev->features = info->net_features; >>> ndev->hw_features = info->net_hw_features; >>> >>> - reset_control_deassert(rstc); >>> + error = reset_control_deassert(rstc); >>> + if (error) { >>> + free_netdev(ndev); >>> + return error; >> >> No, please use *goto* here. And please fix up the order of statements under >> the out_release label before doing that. > > This will lead to a bit more complicated patch, AFAICT. I tried to keep it It's OK! :-) > simple for a fix. Same thing for patch 2. Patch 2 is not as simple as it could have been... [...] MBR, Sergey