mbox series

[v2,0/2] Add support for xhci-sg-trb-cache-size-quirk

Message ID 20231120055803.224634-1-quic_prashk@quicinc.com
Headers
Series Add support for xhci-sg-trb-cache-size-quirk |

Message

Prashanth K Nov. 20, 2023, 5:58 a.m. UTC 
  XHCI_SG_TRB_CACHE_SIZE_QUIRK was introduced in XHCI to resolve
XHC timeout while using SG buffers, which was seen Synopsys XHCs.
The support for this isn't present in DWC3 layer, this series
enables XHCI_SG_TRB_CACHE_SIZE_QUIRK since this is needed for
DWC3 controller.

Changes in v2:
Included xhci-plat.c to pass the quirks via priv data.
Added Fixes tag in device tree binding patch.

Prashanth K (2):
  usb: dwc3: core: Add support for xhci-sg-trb-cache-size-quirk
  dt-bindings: usb: snps,dwc3: Add 'xhci-sg-trb-cache-size-quirk'

 Documentation/devicetree/bindings/usb/snps,dwc3.yaml |  7 +++++++
 drivers/usb/dwc3/core.c                              |  2 ++
 drivers/usb/dwc3/core.h                              |  3 +++
 drivers/usb/dwc3/host.c                              | 10 ++++++++++
 4 files changed, 22 insertions(+)

Comments

Krzysztof Kozlowski Nov. 20, 2023, 9:30 a.m. UTC | #1 
On 20/11/2023 06:58, Prashanth K wrote:
> XHCI_SG_TRB_CACHE_SIZE_QUIRK was introduced in XHCI to resolve
> XHC timeout while using SG buffers, which was seen Synopsys XHCs.
> The support for this isn't present in DWC3 layer, this series
> enables XHCI_SG_TRB_CACHE_SIZE_QUIRK since this is needed for
> DWC3 controller.

You keep Cc-ing incorrect mailing lists (bogus addresses). Just use
get_maintainers.pl  --no-git-fallback without changing its output.

I repeated this comment multiple times to Qualcomm. It's awesome that
Qualcomm participates so much in upstream development, I really
appreciate this. However repeating the same comment over-and-over again,
makes me quite tired. Can you instruct your colleagues to use b4 which
solves this problem? If not, use script like:
https://github.com/krzk/tools/blob/master/linux/.bash_aliases_linux#L91
(or one of many other variants posted by multiple people on the mailing
lists)

Best regards,
Krzysztof
Prashanth K Nov. 21, 2023, 12:34 p.m. UTC | #2 
On 20-11-23 03:00 pm, Krzysztof Kozlowski wrote:
> On 20/11/2023 06:58, Prashanth K wrote:
>> XHCI_SG_TRB_CACHE_SIZE_QUIRK was introduced in XHCI to resolve
>> XHC timeout while using SG buffers, which was seen Synopsys XHCs.
>> The support for this isn't present in DWC3 layer, this series
>> enables XHCI_SG_TRB_CACHE_SIZE_QUIRK since this is needed for
>> DWC3 controller.
> 
> You keep Cc-ing incorrect mailing lists (bogus addresses). Just use
> get_maintainers.pl  --no-git-fallback without changing its output.
> 
> I repeated this comment multiple times to Qualcomm. It's awesome that
> Qualcomm participates so much in upstream development, I really
> appreciate this. However repeating the same comment over-and-over again,
> makes me quite tired. Can you instruct your colleagues to use b4 which
> solves this problem? If not, use script like:
> https://github.com/krzk/tools/blob/master/linux/.bash_aliases_linux#L91
> (or one of many other variants posted by multiple people on the mailing
> lists)
> 
> Best regards,
> Krzysztof
> 



Thanks for your comments! I accidentally added 'yy' in the USB mailing 
list while configuring it. A careless mistake indeed :)

I will resend the the patch without adding the quirk (only driver 
change) since this should be applicable for all the dwc3 devices.

Thanks again,
Prashanth K