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Fri, 17 Nov 2023 11:40:00 +0000 Received: from nalasex01a.na.qualcomm.com (nalasex01a.na.qualcomm.com [10.47.209.196]) by NALASPPMTA01.qualcomm.com (8.17.1.5/8.17.1.5) with ESMTPS id 3AHBdwCg004382 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Fri, 17 Nov 2023 11:39:58 GMT Received: from blr-ubuntu-87.ap.qualcomm.com (10.80.80.8) by nalasex01a.na.qualcomm.com (10.47.209.196) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1118.40; Fri, 17 Nov 2023 03:39:51 -0800 From: Sibi Sankar To: , , , , , CC: , , , , , , , , , , , , , , , , , , Sibi Sankar Subject: [PATCH V2 0/5] dts: qcom: Introduce X1E80100 platforms device tree Date: Fri, 17 Nov 2023 17:09:26 +0530 Message-ID: <20231117113931.26660-1-quic_sibis@quicinc.com> X-Mailer: git-send-email 2.17.1 MIME-Version: 1.0 X-Originating-IP: [10.80.80.8] X-ClientProxiedBy: nasanex01a.na.qualcomm.com (10.52.223.231) To nalasex01a.na.qualcomm.com (10.47.209.196) X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-GUID: fdz1zCHqMhuvRpwAjQL-idsBaHSBgTjd X-Proofpoint-ORIG-GUID: fdz1zCHqMhuvRpwAjQL-idsBaHSBgTjd X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.272,Aquarius:18.0.987,Hydra:6.0.619,FMLib:17.11.176.26 definitions=2023-11-17_09,2023-11-16_01,2023-05-22_02 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 priorityscore=1501 mlxscore=0 spamscore=0 lowpriorityscore=0 clxscore=1015 bulkscore=0 malwarescore=0 phishscore=0 impostorscore=0 mlxlogscore=999 adultscore=0 suspectscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.12.0-2311060000 definitions=main-2311170087 X-Spam-Status: No, score=-2.1 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,SPF_HELO_NONE,SPF_PASS, T_SCC_BODY_TEXT_LINE,URIBL_BLOCKED autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-Greylist: Sender passed SPF test, not delayed by milter-greylist-4.6.4 (snail.vger.email [0.0.0.0]); Fri, 17 Nov 2023 03:40:38 -0800 (PST) X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1782811256776551586 X-GMAIL-MSGID: 1782811256776551586 This series adds the initial (clocks, pinctrl, rpmhpd, regulator, interconnect, CPU, SoC and board compatibles) device tree support to boot to shell on the Qualcomm X1E80100 platform, aka Snapdragon X Elite. Our v1 post of the patchsets adding support for Snapdragon X Elite SoC had the part number sc8380xp which is now updated to the new part number x1e80100 based on the new branding scheme and refers to the exact same SoC. v2: * Update the part number from sc8380xp to x1e80100. * Fixup ordering in the SoC/board bindings. [Krzysztof] * Add pdc node and add wakeup tlmm parent. [Rajendra] * Add cpu/cluster idle states. [Bjorn] * Document reserved gpios. [Konrad] * Remove L1 and add missing props to L2. [Konrad] * Remove region suffix. [Konrad] * Append digits to gcc node. [Konrad] * Add ICC_TAGS instead of leaving it unspecified. [Konrad] * Remove double space. [Konrad] * Leave the size index of memory node untouched. [Konrad] * Override the serial uart with "qcom,geni-debug-uart" in the board files. [Rajendra] * Add additional details to patch 5 commit message. [Konrad/Krzysztof] Dependencies: clks: https://lore.kernel.org/lkml/20231117092737.28362-1-quic_sibis@quicinc.com/ interconnect: https://lore.kernel.org/lkml/20231117103035.25848-1-quic_sibis@quicinc.com/ llcc: https://lore.kernel.org/lkml/20231117095315.2087-1-quic_sibis@quicinc.com/ misc-bindings: https://lore.kernel.org/lkml/20231117105635.343-1-quic_sibis@quicinc.com/ pinctrl: https://lore.kernel.org/lkml/20231117093921.31968-1-quic_sibis@quicinc.com/ rpmhpd: https://lore.kernel.org/lkml/20231117104254.28862-1-quic_sibis@quicinc.com/ Release Link: https://www.qualcomm.com/news/releases/2023/10/qualcomm-unleashes-snapdragon-x-elite--the-ai-super-charged-plat Rajendra Nayak (4): dt-bindings: arm: cpus: Add qcom,oryon compatible dt-bindings: arm: qcom: Document X1E80100 SoC and boards arm64: dts: qcom: Add base X1E80100 dtsi and the QCP dts arm64: defconfig: Enable X1E80100 SoC base configs Sibi Sankar (1): arm64: dts: qcom: x1e80100: Add Compute Reference Device .../devicetree/bindings/arm/cpus.yaml | 1 + .../devicetree/bindings/arm/qcom.yaml | 8 + arch/arm64/boot/dts/qcom/Makefile | 2 + arch/arm64/boot/dts/qcom/x1e80100-crd.dts | 425 ++ arch/arm64/boot/dts/qcom/x1e80100-qcp.dts | 400 ++ arch/arm64/boot/dts/qcom/x1e80100.dtsi | 3509 +++++++++++++++++ arch/arm64/configs/defconfig | 3 + 7 files changed, 4348 insertions(+) create mode 100644 arch/arm64/boot/dts/qcom/x1e80100-crd.dts create mode 100644 arch/arm64/boot/dts/qcom/x1e80100-qcp.dts create mode 100644 arch/arm64/boot/dts/qcom/x1e80100.dtsi