Message ID | 20231102193722.3042245-1-ben.wolsieffer@hefring.com |
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Thu, 02 Nov 2023 12:37:56 -0700 (PDT) Received: from localhost.localdomain ([50.212.55.89]) by smtp.gmail.com with ESMTPSA id a10-20020a0ce90a000000b0065b260eafd9sm30654qvo.87.2023.11.02.12.37.55 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 02 Nov 2023 12:37:56 -0700 (PDT) From: Ben Wolsieffer <ben.wolsieffer@hefring.com> To: linux-spi@vger.kernel.org, devicetree@vger.kernel.org, linux-stm32@st-md-mailman.stormreply.com, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org Cc: Mark Brown <broonie@kernel.org>, Rob Herring <robh+dt@kernel.org>, Krzysztof Kozlowski <krzysztof.kozlowski+dt@linaro.org>, Conor Dooley <conor+dt@kernel.org>, Maxime Coquelin <mcoquelin.stm32@gmail.com>, Alexandre Torgue <alexandre.torgue@foss.st.com>, Alain Volmat <alain.volmat@foss.st.com>, Erwan Leray <erwan.leray@foss.st.com>, Fabrice Gasnier <fabrice.gasnier@foss.st.com>, Ben Wolsieffer <ben.wolsieffer@hefring.com> Subject: [PATCH v2 0/5] Add STM32F7 SPI support Date: Thu, 2 Nov 2023 15:37:17 -0400 Message-ID: <20231102193722.3042245-1-ben.wolsieffer@hefring.com> X-Mailer: git-send-email 2.42.0 MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Spam-Status: No, score=-0.8 required=5.0 tests=DKIM_SIGNED,DKIM_VALID, HEADER_FROM_DIFFERENT_DOMAINS,MAILING_LIST_MULTI,SPF_HELO_NONE, SPF_PASS,T_SCC_BODY_TEXT_LINE autolearn=unavailable autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on agentk.vger.email Precedence: bulk List-ID: <linux-kernel.vger.kernel.org> X-Mailing-List: linux-kernel@vger.kernel.org X-Greylist: Sender passed SPF test, not delayed by milter-greylist-4.6.4 (agentk.vger.email [0.0.0.0]); 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Series | Add STM32F7 SPI support | |
Message
Ben Wolsieffer
Nov. 2, 2023, 7:37 p.m. UTC
This series adds support for SPI on STM32F7 processors. The STM32F7 SPI peripheral is nearly identical to the STM32F4, with the only significant differences being that it supports a wider range of word sizes, and the addition of 32-bit transmit and receive FIFOs. v2: - Add missing commit body Ben Wolsieffer (5): spi: stm32: rename stm32f4_* to stm32fx_* spi: stm32: use callbacks for read_rx and write_tx dt-bindings: spi: add stm32f7-spi compatible spi: stm32: add STM32F7 support ARM: dts: stm32: add SPI support on STM32F746 .../devicetree/bindings/spi/st,stm32-spi.yaml | 1 + arch/arm/boot/dts/st/stm32f746.dtsi | 60 +++ drivers/spi/spi-stm32.c | 455 ++++++++++++------ 3 files changed, 367 insertions(+), 149 deletions(-)
Comments
On Thu, 02 Nov 2023 15:37:17 -0400, Ben Wolsieffer wrote: > This series adds support for SPI on STM32F7 processors. The STM32F7 SPI > peripheral is nearly identical to the STM32F4, with the only significant > differences being that it supports a wider range of word sizes, and the > addition of 32-bit transmit and receive FIFOs. > > v2: > - Add missing commit body > > [...] Applied to https://git.kernel.org/pub/scm/linux/kernel/git/broonie/spi.git for-next Thanks! [1/5] spi: stm32: rename stm32f4_* to stm32fx_* commit: adde8a55daf640515edd78b7ac5f3293c3960b8e [2/5] spi: stm32: use callbacks for read_rx and write_tx commit: 247ba5ea058290824862902f7ee64c20a744c461 [3/5] dt-bindings: spi: add stm32f7-spi compatible commit: 09388379b6d7143ed12fc06900ec9db3bb82ca8f [4/5] spi: stm32: add STM32F7 support commit: a84dcb410b5f928899a53ba79ec71108700872d6 All being well this means that it will be integrated into the linux-next tree (usually sometime in the next 24 hours) and sent to Linus during the next merge window (or sooner if it is a bug fix), however if problems are discovered then the patch may be dropped or reverted. You may get further e-mails resulting from automated or manual testing and review of the tree, please engage with people reporting problems and send followup patches addressing any issues that are reported if needed. If any updates are required or you are submitting further changes they should be sent as incremental updates against current git, existing patches will not be replaced. Please add any relevant lists and maintainers to the CCs when replying to this mail. Thanks, Mark