mbox series

[v5,0/2] riscv: Optimize bitops with Zbb extension

Message ID 20231031064553.2319688-1-xiao.w.wang@intel.com
Headers
Series riscv: Optimize bitops with Zbb extension |

Message

Wang, Xiao W Oct. 31, 2023, 6:45 a.m. UTC 
  Bitops optimization with specialized instructions is common practice in
popular ISAs, this patch set uses RISC-V Zbb extension to optimize four
bitops: __ffs, __fls, ffs and fls.

The first patch rearranges the content in hwcap.h and cpufeature.h, it helps
to avoid a cyclic header including issue for patch 2.

The second patch leverages the alternative mechanism to dynamically apply
this optimization.

Thanks,
Xiao

v5:
- Fix all the checkpatch complaints from "scripts/checkpatch.pl --strict". (Charlie)
  There're three kinds of complaints on patch 2/2 code style:
  * CHECK: Lines should not end with a '('
  * CHECK: spaces preferred around that '-' (ctx:VxV)
  * CHECK: Macro argument reuse 'x' - possible side-effects?
  The third warning on fls(x) macro is fixed alongside with code style improvement.
- Drop the mistakenly added content in v4. (Charlie)
- Link to v4: https://lore.kernel.org/all/20231030063904.2116277-1-xiao.w.wang@intel.com/

v4:
- Simplify the asm code in ffs() and fls() by moving general logic into C
  implementation. (Charlie)
- Add a comment to decorating the large #ifdef block. (Charlie)
- Link to v3: https://lore.kernel.org/all/20230926094655.3102758-1-xiao.w.wang@intel.com/

v3:
- Fix riscv32 build issue reported by kernel test robot. V3 changes "hwcap.h" to
  "cpufeature.h" for files where cpu feature detection APIs are used. (Yujie)
- Link to v2: https://lore.kernel.org/all/20230920074653.2509631-1-xiao.w.wang@intel.com/

v2:
- Remove the "EFI_" prefix from macro name "EFI_NO_ALTERNATIVE" to make it
  generic. (Ard)
- patch-1 is added, it's based on "RISC-V: Enable cbo.zero in usermode". (Andrew)
- Link to v1: https://lore.kernel.org/all/20230806024715.3061589-1-xiao.w.wang@intel.com/

Xiao Wang (2):
  riscv: Rearrange hwcap.h and cpufeature.h
  riscv: Optimize bitops with Zbb extension

 arch/riscv/include/asm/bitops.h       | 254 +++++++++++++++++++++++++-
 arch/riscv/include/asm/cpufeature.h   |  83 +++++++++
 arch/riscv/include/asm/elf.h          |   2 +-
 arch/riscv/include/asm/hwcap.h        |  91 ---------
 arch/riscv/include/asm/pgtable.h      |   1 +
 arch/riscv/include/asm/switch_to.h    |   2 +-
 arch/riscv/include/asm/vector.h       |   2 +-
 arch/riscv/kvm/aia.c                  |   2 +-
 arch/riscv/kvm/main.c                 |   2 +-
 arch/riscv/kvm/tlb.c                  |   2 +-
 arch/riscv/kvm/vcpu_fp.c              |   2 +-
 arch/riscv/kvm/vcpu_onereg.c          |   2 +-
 arch/riscv/kvm/vcpu_vector.c          |   2 +-
 drivers/clocksource/timer-riscv.c     |   2 +-
 drivers/firmware/efi/libstub/Makefile |   2 +-
 drivers/perf/riscv_pmu_sbi.c          |   2 +-
 16 files changed, 347 insertions(+), 106 deletions(-)

Comments

patchwork-bot+linux-riscv@kernel.org Nov. 9, 2023, 10:40 p.m. UTC | #1 
Hello:

This series was applied to riscv/linux.git (for-next)
by Palmer Dabbelt <palmer@rivosinc.com>:

On Tue, 31 Oct 2023 14:45:51 +0800 you wrote:
> Bitops optimization with specialized instructions is common practice in
> popular ISAs, this patch set uses RISC-V Zbb extension to optimize four
> bitops: __ffs, __fls, ffs and fls.
> 
> The first patch rearranges the content in hwcap.h and cpufeature.h, it helps
> to avoid a cyclic header including issue for patch 2.
> 
> [...]

Here is the summary with links:
  - [v5,1/2] riscv: Rearrange hwcap.h and cpufeature.h
    https://git.kernel.org/riscv/c/e72c4333d2f2
  - [v5,2/2] riscv: Optimize bitops with Zbb extension
    https://git.kernel.org/riscv/c/457926b25320

You are awesome, thank you!