mbox series

[v2,00/10] MIPS: Fix kernel in XKPHYS

Message ID 20231027221106.405666-1-jiaxun.yang@flygoat.com
Headers
Series MIPS: Fix kernel in XKPHYS |

Message

Jiaxun Yang Oct. 27, 2023, 10:10 p.m. UTC 
  Hi all,

This series fixes support for loading kernel to XKPHYS space.
It is derived from "MIPS: use virtual addresses from xkphys for MIPS64" [1].

Boot tested on boston and QEMU with loading address set to 0xa800000090000000.
QEMU patch on the way.

For EyeQ5's memory layout, I think you just need to write devicetree memory
node as:

memory@0 {
	device_type = "memory";
	reg = < 0x0 0x08000000 0x0 0x08000000
		0x8 0x08000000 0x0 0x78000000>;
};

And set kernel load addesss to somewhere in RAM, everything should work.

It makes me a little bit confused that in EyeQ5 enablement patch, you set
load address to:
> +else
> +load-$(CONFIG_MIPS_GENERIC)	+= 0xa800000080100000
> +endif
Where does not have memory aviailable.

I guess you might want to set it to 0xa800000800100000?
Though I would suggest you to set it to 0xa800000808000000, to avoid
collisions with low mem and reserved mem.

Gregory and Vladimir, do let me know if I missed anything.

Thanks
- Jiaxun

[1]: https://lore.kernel.org/lkml/20231004161038.2818327-3-gregory.clement@bootlin.com/

Jiaxun Yang (10):
  MIPS: Export higher/highest relocation functions in uasm
  MIPS: spaces: Define a couple of handy macros
  MIPS: genex: Fix except_vec_vi for kernel in XKPHYS
  MIPS: Fix set_uncached_handler for ebase in XKPHYS
  MIPS: Refactor mips_cps_core_entry implementation
  MIPS: Allow kernel base to be set from Kconfig for all platforms
  MIPS: traps: Handle CPU with non standard vint offset
  MIPS: Avoid unnecessary reservation of exception space
  MIPS: traps: Enhance memblock ebase allocation process
  MIPS: Get rid of CONFIG_NO_EXCEPT_FILL

 arch/mips/Kconfig                           |  27 ++--
 arch/mips/include/asm/addrspace.h           |   5 +
 arch/mips/include/asm/mach-generic/spaces.h |   5 +-
 arch/mips/include/asm/mips-cm.h             |   1 +
 arch/mips/include/asm/smp-cps.h             |   4 +-
 arch/mips/include/asm/traps.h               |   1 -
 arch/mips/include/asm/uasm.h                |   2 +
 arch/mips/kernel/cps-vec.S                  | 110 +++++--------
 arch/mips/kernel/cpu-probe.c                |   5 -
 arch/mips/kernel/cpu-r3k-probe.c            |   2 -
 arch/mips/kernel/genex.S                    |  19 ++-
 arch/mips/kernel/head.S                     |   7 +-
 arch/mips/kernel/smp-cps.c                  | 167 +++++++++++++++++---
 arch/mips/kernel/traps.c                    |  85 +++++++---
 arch/mips/mm/uasm.c                         |   6 +-
 15 files changed, 293 insertions(+), 153 deletions(-)

Comments

Gregory CLEMENT Nov. 8, 2023, 4:12 p.m. UTC | #1 
Hello Jiaxun,

> Hi all,
>
> This series fixes support for loading kernel to XKPHYS space.
> It is derived from "MIPS: use virtual addresses from xkphys for MIPS64" [1].
>

Thanks for this new series, I was able to test it this week and I have a
few comments.


> Boot tested on boston and QEMU with loading address set to 0xa800000090000000.
> QEMU patch on the way.
>
> For EyeQ5's memory layout, I think you just need to write devicetree memory
> node as:
>
> memory@0 {
> 	device_type = "memory";
> 	reg = < 0x0 0x08000000 0x0 0x08000000
> 		0x8 0x08000000 0x0 0x78000000>;
> };
>
> And set kernel load addesss to somewhere in RAM, everything should
> work.

With this setup and a workaround that I had to do and I will comment in
for the patch "MIPS: Refactor mips_cps_core_entry implementation", I
managed to boot the kernel and the 8 core of my setup are detected.

>
> It makes me a little bit confused that in EyeQ5 enablement patch, you set
> load address to:
>> +else
>> +load-$(CONFIG_MIPS_GENERIC)	+= 0xa800000080100000
>> +endif
> Where does not have memory aviailable.
>
> I guess you might want to set it to 0xa800000800100000?
> Though I would suggest you to set it to 0xa800000808000000, to avoid
> collisions with low mem and reserved mem.

Indeed I used CONFIG_PHYSICAL_START=0xa800000808000000

Gregory
>
> Gregory and Vladimir, do let me know if I missed anything.
>
> Thanks
> - Jiaxun
>
> [1]: https://lore.kernel.org/lkml/20231004161038.2818327-3-gregory.clement@bootlin.com/
>
> Jiaxun Yang (10):
>   MIPS: Export higher/highest relocation functions in uasm
>   MIPS: spaces: Define a couple of handy macros
>   MIPS: genex: Fix except_vec_vi for kernel in XKPHYS
>   MIPS: Fix set_uncached_handler for ebase in XKPHYS
>   MIPS: Refactor mips_cps_core_entry implementation
>   MIPS: Allow kernel base to be set from Kconfig for all platforms
>   MIPS: traps: Handle CPU with non standard vint offset
>   MIPS: Avoid unnecessary reservation of exception space
>   MIPS: traps: Enhance memblock ebase allocation process
>   MIPS: Get rid of CONFIG_NO_EXCEPT_FILL
>
>  arch/mips/Kconfig                           |  27 ++--
>  arch/mips/include/asm/addrspace.h           |   5 +
>  arch/mips/include/asm/mach-generic/spaces.h |   5 +-
>  arch/mips/include/asm/mips-cm.h             |   1 +
>  arch/mips/include/asm/smp-cps.h             |   4 +-
>  arch/mips/include/asm/traps.h               |   1 -
>  arch/mips/include/asm/uasm.h                |   2 +
>  arch/mips/kernel/cps-vec.S                  | 110 +++++--------
>  arch/mips/kernel/cpu-probe.c                |   5 -
>  arch/mips/kernel/cpu-r3k-probe.c            |   2 -
>  arch/mips/kernel/genex.S                    |  19 ++-
>  arch/mips/kernel/head.S                     |   7 +-
>  arch/mips/kernel/smp-cps.c                  | 167 +++++++++++++++++---
>  arch/mips/kernel/traps.c                    |  85 +++++++---
>  arch/mips/mm/uasm.c                         |   6 +-
>  15 files changed, 293 insertions(+), 153 deletions(-)
>
> -- 
> 2.34.1
>